Non-uniform Feedthrough Configuration for Transistor Outline Package
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Solution Overview
Problem
Transistor outline packages have limited usable surface area on their headers due to their small size, restricting the size of submounts and optoelectronic components that can be placed, despite the increasing demand for space.
Innovation Solution
A feedthrough via and lead configuration is implemented, with two vias of one diameter and four vias of another, arranged in a circular pattern to maximize the usable area on the header interior surface, allowing larger submounts and components to be placed without compromising other design aspects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the header size is increased to provide more usable surface area, then the area for placement of submount and optoelectronic components is improved, but the overall package size and complexity increase
Solution Approach 1:
The patent applies local quality by creating non-uniform via configurations in specific locations on the header. Different via diameters (first and second diameters) are used at different positions, and vias are selectively positioned along circular patterns with different radii. This allows maximum usable surface area to be achieved in the critical submount region without increasing the overall header size, thereby improving local space utilization without increasing global package complexity
Solution Approach 2:
The patent utilizes dimensional arrangement by positioning vias along circular patterns at different radii from the header center. The first set of vias is arranged along a first circular pattern with a first radius, while the second set of vias is arranged along a second circular pattern with a second radius. This circular/dimensional arrangement optimizes the two-dimensional space on the header interior surface, maximizing the usable area for submount placement without requiring a larger overall header diameter
2Quantity of substance
If more vias and leads are added to the header, then the electrical connectivity and component capacity are improved, but the usable surface area for submount placement is reduced
Solution Approach 1:
The patent segments the via and lead configuration into distinct groups with different characteristics. The first group includes vias with a first diameter arranged along a first circular pattern, while the second group includes vias with a second diameter arranged along a second circular pattern. This segmentation allows different regions of the header to serve different functions - some areas optimized for electrical connectivity with multiple leads, while other areas maintain clear space for submount placement
Solution Approach 2:
Different via diameters are used in different locations to optimize local requirements. The first set of vias with the first diameter provides adequate electrical connectivity where needed, while the second set of vias with the second diameter is positioned to maintain optimal spacing. This local differentiation allows the header to accommodate both multiple leads for electrical connectivity and sufficient usable surface area for submount placement
Data Source
AI summary
A transistor outline package having a feedthrough via and lead configuration that maximizes the amount of usable area on a header of the package is disclosed. In one embodiment, the package includes a header having an interior surface that includes a first and second lead assembly. The first lead assembly includes two vias having a first diameter, with each first via being positioned along a first pin circle imaginarily defined on the interior surface of the header. Each first via also includes first leads received therein. The second lead assembly includes four vias having a second diameter each, with each second via being positioned along a second pin circle that has a diameter greater than that of the first pin circle. Each second via includes second leads received therein. This configuration increases usable area on the header interior surface between the leads, enabling relatively larger submounts to be placed thereon.