Nonvolatile Memory 1-3-3 Data Coding for Interference Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional NAND flash memory with 3-bit/Cell configuration faces increased interference between adjacent memory cells, leading to precision challenges and higher bit error rates due to the larger number of threshold voltage regions and increased electric field interference, which affects writing and reading speeds and requires complex error correction mechanisms.
Innovation Solution
Implementing a 1-3-3 data coding scheme that divides the data writing process into three stages, with specific threshold voltage boundaries for each page, reducing interference by ensuring that each stage completes before data can be read, and optimizing the memory controller to manage data across multiple pages efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If 3-bit/Cell configuration is used to increase storage density, then storage capacity is improved, but interference between adjacent memory cells increases and threshold voltage adjustment precision requirements increase
Solution Approach 1:
The patent divides the data writing process into three distinct stages (first stage program, second stage program, third stage program), where each stage writes to specific pages (first page, second and third pages) with different boundary conditions. This segmentation allows precise control of threshold voltage regions for each page independently, reducing interference between adjacent memory cells while maintaining 3-bit/Cell storage capacity.
Solution Approach 2:
The patent applies different boundary conditions for different pages: the first page uses one boundary while the second and third pages use three boundaries each. This local differentiation allows optimized threshold voltage regions for each page, enabling precise data representation without uniform treatment that would increase cross-cell interference.
2Quantity of substance
If 3-bit/Cell configuration is used to increase storage density, then storage capacity is improved, but threshold voltage adjustment precision requirements increase
Solution Approach 1:
By segmenting the programming process into three stages with specific boundary conditions for each page, the patent creates distinct threshold voltage regions that are easier to control and adjust precisely during manufacturing, rather than requiring uniform precision across all possible threshold values.
Solution Approach 2:
The patent performs preliminary programming stages that establish boundary conditions before final data writing. The first stage programs the first page with one boundary, and subsequent stages program the second and third pages with three boundaries each, establishing a hierarchical structure that simplifies precision requirements for subsequent adjustments.
3Quantity of substance
If multiple threshold voltage regions are used for 3-bit data storage, then storage capacity is improved, but bit error rates increase
Solution Approach 1:
The patent segments the 3-bit data into three pages with different boundary conditions (one boundary for first page, three boundaries for second and third pages). This creates well-defined threshold voltage regions that reduce ambiguity and reading errors, thereby lowering bit error rates while maintaining high storage capacity.
Solution Approach 2:
The patent incorporates verification steps after each programming stage to ensure correct data writing. The memory controller verifies the programmed data and can reprogram if necessary, providing feedback that reduces bit error rates by catching and correcting errors before they occur.
4Productivity
If conventional data writing is used, then writing speed is maintained, but interference between adjacent cells increases and requires complex error correction
Solution Approach 1:
By segmenting the writing process into three stages with specific boundary conditions, the patent reduces interference between adjacent cells, which in turn reduces the need for complex error correction mechanisms. The structured approach to programming creates more reliable data storage that requires simpler error handling.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces bit error rates, enhances writing speed, and minimizes the capacity requirements of the write buffer, improving overall memory device performance and reducing power consumption by allowing for non-sequential programming and reading across multiple stages.
Implementation Method 1
information is stored as an amount of electric charge in each of floating gates of memory cells
Implementation Method 2
Each memory cell has a threshold voltage according to an amount of electric charge
Implementation Method 3
Electric charge is injected so that the threshold voltage of the memory cell is in a region corresponding to the data value to be stored
Data Source
AI summary
According to one embodiment, a nonvolatile memory includes a memory cell array having a plurality of memory cells configured to store 3-bit data corresponding to first to third pages. Data coding, in which first page data values have one boundary, and second and three page data values each have three boundaries, is used to perform a first stage program based on data written into first page d, a second stage program based on data written into the first, second, and third pages, and a third stage program based on data written into the first, second, and third pages.