Nonvolatile Memory Bit Line Switch Segmentation
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Solution Overview
Problem
Current nonvolatile memory devices face challenges in precisely reading data from memory cell arrays due to issues with electrical coupling and precharging operations, which can lead to inaccurate data sensing and storage.
Innovation Solution
A nonvolatile memory apparatus comprising a first and second memory cell array electrically coupled through a bit line switch, with a data sensing circuit that precharges nodes based on power-up signals and generates output signals by changing voltage levels, allowing for precise data reading and isolation during operation periods.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the first memory cell array and second memory cell array are electrically coupled through a bit line switch, then data reading precision is improved, but device complexity increases
Solution Approach 1:
The memory system is divided into two separate memory cell arrays (first and second arrays) that can be independently managed. The bit line switch segments the bit line into separate paths, allowing selective coupling between arrays. This segmentation enables precise control over which array is accessed, improving reading precision while managing complexity through modular organization.
Solution Approach 2:
The bit line switch acts as an intermediary component between the first and second memory cell arrays. It controls the electrical coupling state, enabling or disabling connections based on operational requirements. This intermediary mechanism allows precise data reading by ensuring only the intended array is electrically connected during sensing operations.
2Measurement precision
If the data sensing circuit precharges the sensing node based on power-up signals, then voltage level sensing accuracy is improved, but the precharging operation time increases
Solution Approach 1:
The sensing node is precharged to a predetermined voltage level before the actual sensing operation begins. This preliminary action ensures that the sensing circuit starts from a known state, improving voltage level detection accuracy. The precharging is performed during power-up or before read operations, preparing the circuit in advance for precise measurements.
Solution Approach 2:
The precharging operation is performed periodically or at specific intervals (such as during power-up or before each read cycle). This periodic precharging maintains the sensing node at the correct voltage level, ensuring consistent sensing accuracy without requiring continuous charging, thus optimizing the balance between precision and time consumption.
3Reliability
If the bit line switch electrically isolates memory cell arrays during operation, then data storage reliability is improved, but the switching operation complexity increases
Solution Approach 1:
The bit line switch extracts or separates the electrical connection between the first and second memory cell arrays when isolation is required. By taking out the electrical coupling, the system prevents interference or unwanted interactions between arrays, improving data storage reliability. The switch enables selective disconnection, ensuring that only the active array is accessed while the other remains isolated.
4Measurement precision
If the data sensing circuit changes voltage level of the output node according to sensing node voltage, then data sensing accuracy is improved, but power consumption increases
Solution Approach 1:
The data sensing circuit changes the voltage level parameter of the output node based on the sensed voltage level from the sensing node. This parameter transformation enables accurate data representation by mapping the sensing node voltage to appropriate output voltage levels. The circuit selectively adjusts voltage levels only when sensing operations are performed, balancing accuracy requirements with power consumption considerations.
Data Source
AI summary
A nonvolatile memory apparatus and an operating method of the nonvolatile memory apparatus may include a first memory cell array, a second memory cell array, a bit line switch, and a sensing control signal generation circuit. The first and second memory cell arrays may be coupled to a bit line. The bit line switch may electrically couple the first memory cell array to the second memory cell array according to an operation period of the non-volatile memory apparatus.