Nonvolatile Memory Voltage Control for Fast Programming

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

Nonvolatile memory devices with multi-level cells face challenges in reducing the time required for program and verification operations, particularly when using negative voltage distributions, which can increase the complexity and duration of these processes.

Innovation Solution

The implementation of a nonvolatile memory device with a voltage control unit that supplies a first negative voltage to global word lines and charges the bulk region of transistors with a second negative voltage, optimizing the voltage distribution for faster program and verification operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If negative voltage distribution is used to increase margin between program states, then reliability is improved, but operation time increases

Engineering Contradiction:

Improvemargin between program statesVSAvoidprogram and verification operation time

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The bulk region of the transistor is pre-charged with a second negative voltage before the program operation begins. This preliminary charging of the bulk region prepares the transistor for faster switching and reduces the time required during the actual program and verification operations, while maintaining the reliability benefits of negative voltage distribution.

Inventive Principle:

Principle #10Preliminary action

2Productivity

If high program voltages are applied to program memory cells, then programming speed is improved, but device damage risk increases

Engineering Contradiction:

Improveprogramming speedVSAvoiddevice damage from high voltages

Core Design Contradiction:

ProductivityVSObject-affected harmful factors

Solution Approach 1:

The transistor bulk region acts as an intermediary element between the high program voltage applied to the gate and the memory cell. By pre-charging the bulk region with a negative voltage, the transistor is prepared to handle the high voltage stress more effectively, enabling faster programming while reducing the risk of device damage through controlled voltage distribution.

Inventive Principle:

Principle #24Intermediary (Mediator)

Data Source

PatentUS8559227B2Nonvolatile memory device

Publication Date: 2013.10.15 MIMIRIP LLC

AI summary

A nonvolatile memory device includes a plurality of global word lines, a plurality of transistors configured to transfer voltages of the global word lines to a plurality of local word lines inside a cell block, and a voltage control unit configured to supply a first negative voltage to a global word line of the plurality of global word lines and configured to charge a bulk region of the plurality of transistors with a second negative voltage.