Nonvolatile Memory Cell With Integrated Transistor Current Limiting
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Solution Overview
Problem
Existing nonvolatile semiconductor storage devices, such as ReRAM, face challenges in scaling memory size while preventing damage from large currents, requiring additional components like diodes or transistors to limit current, which complicates integration into CMOS logic processes.
Innovation Solution
A memory array circuit utilizing a single field-effect transistor (FET) and a metal-insulator-metal (MIM) storage device with an oxide-based dielectric layer, where the resistivity is adjusted by voltages applied to word and bit lines, simplifying integration into CMOS logic processes and enhancing embedded applications.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If diodes or transistors are used to limit current in ReRAM, then the resistance storage element is protected from damage, but the device complexity increases
Solution Approach 1:
The patent combines the current-limiting function with the memory storage function by using a single transistor to control both aspects. The transistor's gate is connected to the bottom electrode of the MIM structure, allowing the same component to regulate current flow while the MIM structure stores data, eliminating the need for separate current-limiting diodes or transistors.
Solution Approach 2:
The transistor in the patent serves multiple functions: it acts as a switch for data access, a current limiter to protect the MIM structure, and part of the memory cell itself. This multi-functional design reduces overall device complexity while maintaining reliability.
2Reliability
If additional components like diodes or transistors are added to limit current, then current control is improved, but ease of manufacture decreases
Solution Approach 1:
The patent merges the current control function into the existing transistor component that is already part of standard CMOS fabrication processes. By connecting the transistor gate to the MIM bottom electrode, the design utilizes conventional CMOS components and processes without requiring additional specialized manufacturing steps for current-limiting structures.
3Productivity
If cross-bar array with diodes is used to scale memory size, then memory density increases, but device complexity increases
Solution Approach 1:
The patent employs a cross-bar array architecture where memory cells are formed at the intersections of word lines and bit lines. Each intersection contains a MIM structure with an integrated transistor, combining the storage and control functions in a single location. This allows for high-density memory scaling without proportionally increasing control circuit complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration allows for efficient resistivity adjustment and data storage in a simplified structure, facilitating easier integration into CMOS logic processes and making it more suitable for embedded applications by eliminating the need for additional current-limiting components.
Implementation Method 1
The resistivity of the storage device is configured to be adjusted according to a first voltage applied to the word line and a second voltage applied to the bit line
Data Source
AI summary
A memory cell and the associated array circuits are disclosed. The memory array circuit includes a plurality of memory units, in which each of the memory units includes a storage device and a field-effect transistor. The storage device includes a top electrode, a bottom electrode and an oxide-based dielectric layer. The top electrode is formed by metal or metallic oxide dielectrics and connected to a word line. The bottom electrode is formed by metal, and the oxide-based dielectric layer is placed between the top electrode and the bottom electrode. The field-effect transistor includes a gate terminal connected to the bottom electrode, a source terminal connected to a ground line, and a drain terminal connected to a bit line. The resistance of the storage device is configured to be adjusted according to a first voltage applied to the word line and a second voltage applied to the bit line.