Non-volatile Memory Control Circuit Parallel Error Detection
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Solution Overview
Problem
Existing non-volatile memory systems face challenges in quickly and accurately retrieving configuration data during power-on or reset events due to potential errors in data storage, particularly in fuse-based systems where bit cells may misread logic high as logic low, leading to incorrect initialization of integrated circuits.
Innovation Solution
A non-volatile storage circuit with a primary and redundant copy of data values, where an error detection circuit performs parallel error correction and detection operations using bitwise logical-OR and XOR functions to generate accurate data outputs and error signals, ensuring correct initialization of integrated circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional single-copy data storage is used in non-volatile memory, then device complexity is reduced, but data retrieval accuracy deteriorates due to potential bit cell misreading errors
Solution Approach 1:
The patent stores redundant copies of configuration data in multiple storage locations within the non-volatile memory. During power-on, the error detection circuit retrieves and compares these copies to identify and correct bit cell misreading errors, thereby improving data retrieval accuracy without requiring external correction mechanisms
Solution Approach 2:
The error detection circuit acts as an intermediary between the non-volatile memory and the rest of the system. It performs error detection and correction operations on retrieved data before passing it to the system logic, isolating the impact of potential read errors and preventing incorrect initialization
2Loss of time
If sequential error detection and correction operations are performed, then circuit complexity is reduced, but initialization time increases
Solution Approach 1:
The error detection circuit performs parallel error detection and correction operations simultaneously during the power-on initialization sequence. Multiple error detection paths operate in parallel to evaluate different error scenarios, enabling rapid error identification and correction without extending initialization time
Solution Approach 2:
The error detection and correction logic is pre-configured in the circuit during manufacturing. When data is retrieved from non-volatile memory, the correction operations are immediately applied based on pre-established error detection rules, eliminating the need for iterative error checking and reducing initialization delay
Data Source
AI summary
An apparatus includes a non-volatile storage circuit that includes a primary copy of a data value in a first storage location and a redundant copy of the data value in a second, different storage location. The data value includes one or more bits. The apparatus further includes an error detection circuit configured to retrieve contents of the first and second storage locations in response to a request for the data value. The error detection circuit is further configured to perform an error correction operation on the retrieved contents of the first and second storage locations to generate a data output responsive to the request, and to perform an error detection operation to generate an error signal that indicates whether the retrieved contents of the first and second storage locations are different.