Nonvolatile Memory Controller Common Write Operation

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Highly integrated semiconductor storage devices face reliability issues due to increased manufacturing complexity, which affects the consistency and efficiency of write operations across multiple pages.

Innovation Solution

A storage device with a controller that performs a common write operation on multiple pages by detecting a common data group and applying it simultaneously, followed by individual write operations on each page, using a program loop with adjustable voltages to optimize data distribution and reduce stress on memory cells.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If a common write operation is performed on multiple pages simultaneously, then write operation efficiency is improved, but write accuracy and reliability may deteriorate due to increased complexity in managing multiple data groups

Engineering Contradiction:
Improvewrite operation efficiencyVSAvoidwrite operation reliability
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The write operation is divided into two distinct phases: a common write operation that handles shared data across multiple pages, and individual write operations that handle page-specific data. This segmentation allows the system to maintain high throughput through parallel common writes while ensuring accuracy through subsequent individual writes that can be verified and corrected independently.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The common write operation is performed as a preliminary action before individual write operations. By first writing the common data group to all relevant pages simultaneously, the system prepares the baseline data structure efficiently, then proceeds with individual page writes to complete the operation. This preliminary action reduces overall write time while maintaining data integrity.

Inventive Principle:
Principle #10Preliminary action

2Ease of manufacture

If high degree of integration is implemented to reduce manufacturing cost, then manufacturing cost decreases, but device reliability deteriorates due to increased complexity

Engineering Contradiction:
Improvemanufacturing costVSAvoiddevice reliability
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The common write operation mechanism serves multiple functions: it efficiently writes shared data across multiple pages simultaneously, reduces overall write time, and maintains data consistency across pages. This multi-functional approach allows the storage device to achieve high integration benefits without proportionally increasing complexity, as the same write mechanism handles both common and individual write operations.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The system dynamically adjusts write operation parameters by switching between common write mode (for shared data) and individual write mode (for page-specific data). This parameter change strategy allows the device to optimize performance and reliability based on the specific write scenario, maintaining high integration benefits while managing complexity through adaptive operation modes.

Inventive Principle:
Principle #35Parameter changes

3Speed

If program voltage is increased to improve write speed, then write operation speed increases, but stress on memory cells increases reducing reliability

Engineering Contradiction:
Improvewrite operation speedVSAvoidmemory cell reliability
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The common write operation applies program voltage to multiple pages simultaneously for speed, but the subsequent individual write operations apply targeted voltage only where needed. This partial action approach ensures that not all memory cells undergo high-stress programming at once, reducing cumulative stress while maintaining overall write speed through the efficient common write phase.

Inventive Principle:
Principle #16Partial or excessive action

Solution Approach 2:

The write process uses periodic action by alternating between common write operations (applying program voltage to multiple pages) and individual write operations (applying voltage to specific pages). This periodic pattern allows memory cells to experience high voltage in controlled intervals rather than continuously, reducing cumulative stress while maintaining write speed through efficient periodic programming cycles.

Inventive Principle:
Principle #19Periodic action

Data Source

PatentUS10121543B2Storage device including a nonvolatile memory device and a controller for controlling a write operation of the nonvolatile memory device and an operating method of the storage device
Publication Date: 2018.11.06 SAMSUNG ELECTRONICS CO LTD
  • US10121543B2 patent drawing
  • US10121543B2 patent drawing
  • US10121543B2 patent drawing

AI summary

A storage device includes a nonvolatile memory device including a plurality of memory cells, the memory cells divided into a plurality of pages, and a controller configured to control the nonvolatile memory device. The storage device is configured to collect two or more write data groups to be written to two or more pages, to simultaneously perform a common write operation with the two or more pages based on the two or more write data groups, and to sequentially perform an individual write operation with each of the two or more pages based on the two or more write data groups.