Nonvolatile Memory Device Deep Channel Structure
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Solution Overview
Problem
Nonvolatile memory devices face challenges in increasing integration and operating speed while reducing operating current, as higher current density is required for phase change memory devices, leading to potential short channel effects and limitations in variable resistance.
Innovation Solution
A method for operating nonvolatile memory devices in a multi-bit mode by programming and reading 2-bit data in adjacent resistance layers, using buried electrodes and a gate electrode to control current flow, allowing for lower operating current and increased integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If higher current density is applied to change the crystal state of phase change memory device, then data storage capability is improved, but operating current increases and short channel effect occurs
Solution Approach 1:
The patent applies local quality by creating a deep channel structure that concentrates current flow in a specific region beneath the resistance layer. This localized current concentration enables effective crystal state change in the phase change material without requiring high overall current density, thus resolving the contradiction between data storage capability and operating current consumption.
Solution Approach 2:
The patent introduces a vertical dimension by forming a deep channel that extends downward from the resistance layer to the buried electrode. This three-dimensional current path allows current to be delivered efficiently to the phase change region without increasing lateral current density, thereby maintaining data storage capability while reducing operating current and avoiding short channel effects.
2Productivity
If integration of nonvolatile memory devices is increased, then capacity is improved, but operating current must be reduced which affects variable resistance of resistance nodes
Solution Approach 1:
The patent segments the current path into distinct regions: a deep channel region for efficient current delivery and a lateral region for bit line connections. This segmentation allows the memory device to achieve high integration capacity while maintaining adequate operating current through the optimized deep channel structure, resolving the contradiction between integration and current consumption.
3Use of energy by moving object
If region of phase change resistance element is reduced to obtain higher current density, then operating current is reduced, but area for data storage is decreased
Solution Approach 1:
The patent resolves this contradiction by transitioning from a two-dimensional current distribution to a three-dimensional deep channel structure. The deep channel concentrates current vertically beneath the resistance layer, enabling high current density in the storage region without reducing the lateral area of the resistance element, thus maintaining both low operating current and adequate storage area.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables efficient data storage and retrieval in a multi-bit mode with reduced operating current, enhancing integration and operating speed of nonvolatile memory devices without generating short channel effects.
Implementation Method 1
forming a deep channel to connect one of the buried electrodes with one of the adjacent resistance layers
Implementation Method 2
each of which may store a variable resistance state
Data Source
AI summary
A nonvolatile memory device may be operated in a multi-bit mode at a lower operating current and with higher integrated of the memory device. A first buried electrode may be used as a first bit line, a second buried electrode may be used as a second bit line, and/or a gate electrode may be used as a word line. First and second resistance layers may be programmed with 2-bit data and the 2-bit data may be read from the first and second resistance layers. More than 2-bit data may be programmed and read using more than 2 buried electrodes.