Nonvolatile Memory Dual-Pulse Programming Without Bit Line Forcing
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Solution Overview
Problem
In nonvolatile memory devices, managing threshold voltage distributions for multi-level cell (MLC) memory cells during programming and reading operations is crucial for data reliability, but existing methods often widen these distributions due to bit line forcing, leading to data accuracy issues.
Innovation Solution
A method involving a dual-pulse programming approach with a 2-step verification operation, where a first pulse and a second pulse with a lower voltage level are applied to memory cells based on their threshold voltages, without using bit line forcing, to accurately program and verify memory cells, thereby maintaining a precise threshold voltage distribution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If bit line forcing is used during programming, then programming speed is improved, but threshold voltage distribution widens leading to data accuracy degradation
Solution Approach 1:
The patent segments the programming process into multiple program loops with incremental voltage steps. Instead of applying a single high-voltage pulse that forces bit lines, the method applies multiple lower-voltage pulses in sequence (e.g., Vpgm1, Vpgm2, Vpgm3 increasing by 2-5V each loop), allowing gradual threshold voltage adjustment without bit line forcing, thus maintaining tight voltage distributions while achieving programming goals
Solution Approach 2:
The patent dynamically changes programming parameters across multiple loops: verification voltages (Vfy1, Vfy2, Vfy3) are incrementally increased alongside program voltages, and pulse widths are adjusted based on verification results. This parameter adaptation allows precise control of threshold voltage without excessive bit line forcing, resolving the contradiction between speed and precision
2Ease of operation
If single-level verification is used, then verification simplicity is improved, but data reliability deteriorates due to inability to accurately manage threshold voltage distributions
Solution Approach 1:
The patent divides verification into multiple discrete steps with different verification voltages (Vfy1 for lower threshold range, Vfy2 for upper threshold range). Each verification step checks a specific portion of the threshold voltage distribution, providing comprehensive reliability assessment while maintaining clear, systematic operation through structured multi-step verification
Solution Approach 2:
The patent implements feedback control where verification results from each step determine subsequent programming actions. If verification fails at a given voltage level, the system adjusts program voltage and retry count, then re-verify. This closed-loop feedback ensures data reliability while maintaining operational simplicity through automated decision-making based on verification outcomes
3Productivity
If high program voltage pulses are applied to all selected memory cells, then programming coverage is improved, but threshold voltage distribution widens due to unnecessary programming of cells already at target voltage
Solution Approach 1:
The patent performs preliminary verification before applying high-voltage program pulses. By first applying lower verification voltages and checking which cells need programming, the system avoids unnecessary high-voltage application to cells already at target threshold voltage. This preliminary assessment prevents distribution widening while ensuring all cells requiring programming receive appropriate voltage
Solution Approach 2:
The patent applies different program voltage levels to different groups of selected memory cells based on their individual threshold voltage states. Cells verified to be below target voltage receive appropriate program pulses, while cells already at or above target voltage receive no additional programming. This localized quality control maintains tight threshold voltage distributions across the entire selected block
Data Source
AI summary
A programming method includes a first program loop applying first and second pulses to a selected word line and thereafter determining a threshold voltage for the selected memory cell in relation to first and second verification voltages. Then, upon determining that the threshold voltage is lower than the first verification voltage, performing the second program loop by applying the first pulse to the selected word line, or upon determining that the threshold voltage is higher than the first verification voltage and lower than the second verification voltage, performing the second program loop by applying the second pulse to the selected word line.