Nonvolatile Memory Bit Line Precharging via Dynamic Connection Unit
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Solution Overview
Problem
Conventional nonvolatile memory devices require a two-step precharge operation for bit lines, increasing precharge time and reducing operating speed due to the need for different voltage levels based on memory cell states and programming status.
Innovation Solution
A nonvolatile memory device that precharges bit lines with different voltages in a single step based on the state of the memory cell and its programming status, using a page buffer to drive sensing nodes to ground, middle, or core voltages, and connection units to couple bit lines to sensing nodes in response to control signals, allowing simultaneous precharging of all bit lines regardless of their states.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a two-step precharge operation is used to precharge bit lines with different voltage levels based on memory cell states, then the precharge operation can accommodate different programming conditions, but the precharge time increases and operating speed decreases
Solution Approach 1:
The patent applies dynamics by making the connection unit's control signal voltage dynamic rather than fixed. The control signal can take different voltage levels (first voltage or second voltage) depending on the memory cell state and programming status, allowing the precharge operation to adapt to different conditions without requiring separate precharge steps for each condition.
Solution Approach 2:
The connection unit is designed to perform multiple functions by responding to different control signal voltages. A single connection unit can handle both normal program operations and slow program operations by adjusting its behavior based on the control signal voltage level, eliminating the need for separate precharge circuits for different operation modes.
2Adaptability or versatility
If a two-step precharge operation is used to precharge bit lines with different voltage levels based on memory cell states, then the precharge operation can accommodate different programming conditions, but the precharge time increases
Solution Approach 1:
The connection unit responds dynamically to control signal voltages, allowing it to adjust its precharge behavior in real-time based on the memory cell state. This dynamic response enables a single precharge step to replace what would otherwise require two separate precharge steps, reducing precharge time while maintaining adaptability.
Solution Approach 2:
The connection unit is configured to respond to control signal voltages that are generated based on predetermined conditions (memory cell state and programming status). This preliminary configuration allows the system to prepare the appropriate precharge voltage in advance, eliminating the need for sequential precharge operations and reducing overall precharge time.
3Measurement precision
If different voltage levels are applied to sensing nodes based on memory cell states and programming status, then accurate program verification can be achieved, but the device complexity increases
Solution Approach 1:
The connection unit serves as a universal component that handles both normal and slow program operations through a single structure. By making the connection unit responsive to different control signal voltage levels, the patent achieves multi-functionality without duplicating hardware, thus maintaining program verification accuracy while avoiding increased device complexity.
Solution Approach 2:
The patent changes the voltage parameter of the control signal to differentiate between normal and slow program operations. Instead of using different hardware configurations or multiple connection units, the system varies the control signal voltage level (first voltage or second voltage) to achieve the desired precharge behavior, maintaining simplicity while ensuring accurate program verification.
Data Source
AI summary
A nonvolatile memory device may include a cell string comprising a plurality of memory cells coupled in series; a bit line coupled to the cell string; a page buffer suitable for driving a sensing node to a ground voltage, a middle voltage, and a core voltage during a normal program operation, a slow program operation and a program inhibition operation, respectively; and a connection unit suitable for coupling the bit line to the sensing node in response to a control signal of a first voltage during the slow program operation, and in response to the control signal of a second voltage higher than the first voltage during the normal program operation and the program inhibition operation.