Nonvolatile Memory Fast Read Page Control Logic
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Solution Overview
Problem
Existing nonvolatile memory devices face challenges in efficiently storing multiple data bits per memory cell while maintaining reliability, leading to storage space loss when using single level cell programming across an entire memory block.
Innovation Solution
A nonvolatile memory device with a memory cell array featuring cell strings where at least one memory cell is a multi-level cell storing three bits, and a control logic circuit that reads fast read pages with one read voltage and normal read pages with the same number of read voltages, optimizing data retrieval and storage efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multi-level cell programming is used to store multiple data bits per memory cell, then storage capacity is improved, but data reliability deteriorates
Solution Approach 1:
The memory block is divided into multiple memory regions, where each region can be independently programmed with different cell types (SLC or MLC). This segmentation allows the system to allocate SLC regions for high-reliability data and MLC regions for capacity-oriented storage, resolving the contradiction between storage capacity and data reliability by spatial separation of functions.
2Reliability
If single level cell programming is used across an entire memory block to maintain reliability, then data reliability is improved, but storage space is lost
Solution Approach 1:
Different memory regions within the same memory block are assigned different programming modes based on local requirements. SLC programming is applied locally to regions requiring high reliability, while MLC programming is applied locally to regions prioritizing storage capacity. This local quality differentiation eliminates the need to convert the entire memory block to SLC mode, thereby preserving storage space while maintaining reliability where needed.
3Speed
If fast read page is read with one read voltage to improve read speed, then read speed is improved, but device complexity increases
Solution Approach 1:
The control logic circuit dynamically adjusts the read operation mode based on the programming mode of the target memory region. When reading from an SLC-programmed region, the control logic activates a simplified single-voltage read mode for high speed. When reading from an MLC-programmed region, it switches to a multi-voltage read mode. This dynamic adaptation allows the system to optimize read speed for fast read pages while managing device complexity through context-aware control.
Data Source
AI summary
A nonvolatile memory device including: a memory cell array, the memory cell array including a plurality of cell strings, at least one of the cell strings including a plurality of memory cells stacked in a direction perpendicular to a surface of a substrate, at least one of the memory cells is a multi-level cell storing at least three bits; and a control logic circuit configured to control a page buffer to read a fast read page of the memory cells with one read voltage and at least two normal read pages of the memory cells with the same number of read voltages.