Non-volatile Memory Metal Control Gate Damascene Fabrication
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Solution Overview
Problem
Conventional flash memory devices face challenges in achieving improved performance, reliability, and memory location density due to parasitic electrical properties such as resistance and capacitance, which can lead to slower operation and increased complexity in fabrication processes.
Innovation Solution
The proposed solution involves a damascene gate process and reoxidation techniques to fabricate metal control gates with improved alignment and reduced resistivity, along with the use of non-metallic materials and dielectric layers to minimize parasitic electrical properties, and the substitution of metal gates like Tungsten or Cobalt for WSi2 to enhance manufacturability and reduce etching risks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional fabrication processes are used, then manufacturing simplicity is maintained, but parasitic resistance and capacitance increase leading to slower operation
Solution Approach 1:
The control gate is segmented into multiple metal layers (first control gate metal layer and second control gate metal layer) with different functionalities. The first layer provides low resistance for fast operation, while the second layer provides etch selectivity and protection. This segmentation allows the device to achieve high speed performance without requiring a complete redesign of the fabrication process.
Solution Approach 2:
The control gate structure uses composite materials combining different metals (e.g., tungsten and cobalt) with distinct properties. Tungsten provides low resistivity for fast operation, while cobalt provides etch resistance. This composite approach reduces parasitic resistance and capacitance to improve speed while maintaining compatibility with existing fabrication processes.
2Reliability
If metal gates like Tungsten or Cobalt are used, then etching risk is reduced, but manufacturing complexity increases
Solution Approach 1:
A sacrificial nitride layer is introduced as an intermediary between the metal control gate layers and the etching process. This nitride layer serves as a protective mask during etching operations, preventing damage to the metal gates. After etching, the sacrificial layer is removed, leaving the metal gates intact. This intermediary approach enhances etching resistance while maintaining ease of manufacture by using a well-established sacrificial layer technique.
3Ease of manufacture
If WSi2 is used for control gate, then manufacturing is easier, but etching damage risk increases
Solution Approach 1:
The patent replaces the durable but etch-vulnerable WSi2 control gate with a structure using metal layers (tungsten, cobalt) that are more resistant to etching damage. The sacrificial nitride layer acts as a disposable protective element that is removed after serving its purpose. This substitution reduces etching damage risk while maintaining manufacturability through standard metal deposition and etching processes.
4Speed
If parasitic resistance is reduced, then operation speed increases, but fabrication precision requirements increase
Solution Approach 1:
Different regions of the control gate structure are assigned different metal materials with optimized local properties. The first control gate metal layer uses low-resistivity metal (tungsten) in regions where current flow is highest to minimize parasitic resistance. The second layer uses metal with etch resistance (cobalt) in regions requiring protection. This local quality approach reduces overall parasitic resistance while managing fabrication precision requirements through targeted material placement.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in reduced parasitic resistance and capacitance, leading to faster and more reliable flash memory device performance with improved manufacturability and reduced risk of etching damage, while maintaining dielectric quality and alignment of layers for enhanced electrical flow.
Implementation Method 1
Certain fabrication techniques may include, for example, depositing a tunnel layer over a substrate
Implementation Method 2
depositing a tunnel layer over a substrate, a first control gate metal layer over the tunnel layer, and a first dielectric layer over the first control gate metal layer
Implementation Method 3
reoxidation techniques to fabricate metal control gates with improved alignment and reduced resistivity
Data Source
AI summary
Briefly, embodiments of non-volatile memory and embodiments of fabrication thereof are disclosed. For example, a non-volatile memory device having a gate assembly with a floating gate and a control gate assembly is described. The control gate assembly includes a non-metal conductive control gate and a metal control gate in one embodiment. Additional embodiments are described, including use of a sacrificial nitride layer and forming contact recesses to create source or drain contacts, as other examples.