Non-Volatile Memory Read Circuit for Transistor Mismatch Compensation
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Solution Overview
Problem
Non-volatile memories with reduced memory element sizes experience increased mismatch in transistor characteristics, leading to instability and improper data storage and read operations.
Innovation Solution
A non-volatile memory design that includes a first and second transistor, a third transistor connected to the gate of the second transistor, a fourth transistor connected to the gate of the first transistor, and a supply circuit to provide drain currents, with a signal output circuit determining the read operation based on drain currents to mitigate mismatch effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the sizes of the memory elements (first and second transistors) are reduced to reduce the entire circuit size, then the circuit size is reduced, but the mismatch of characteristics between the memory elements increases
Solution Approach 1:
The patent introduces a compensation circuit comprising a third transistor and a fourth transistor that acts as an intermediary to detect and compensate for the mismatch between the first and second transistors. The compensation circuit generates compensation signals that are fed back to adjust the gate voltages of the memory transistors, thereby offsetting the characteristic mismatch caused by size reduction.
Solution Approach 2:
The patent implements a feedback mechanism where the compensation circuit continuously monitors the drain current difference between the first and second transistors and adjusts the gate voltages accordingly. The compensation circuit uses the third and fourth transistors to sense the mismatch and generates feedback signals that are applied to the memory transistors to maintain balanced characteristics despite size scaling.
2Reliability
If the drain current of the second transistor is made larger than that of the first transistor in the initial state to prevent unstableness of stored data, then the stability of stored data is improved, but the mismatch sensitivity increases
Solution Approach 1:
The compensation circuit provides continuous feedback to dynamically adjust the gate voltages of the first and second transistors, ensuring that their drain currents remain balanced even when operating with larger current margins for stability. The feedback mechanism detects any drift or mismatch and corrects it in real-time, maintaining both stability and low sensitivity to manufacturing variations.
Solution Approach 2:
The patent dynamically changes the gate voltage parameters of the memory transistors based on the operating conditions and detected mismatch levels. By adjusting these parameters through the compensation circuit, the system can optimize the balance between current margin for stability and sensitivity to mismatch, adapting to different operational states.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design provides a non-volatile memory that is less affected by transistor mismatch, ensuring stable data storage and read operations, allowing for optimal design and easy margin inspection.
Implementation Method 1
a supply circuit configured to be capable of supplying drain currents to the third and fourth transistors
Implementation Method 2
the signal output circuit is configured to output a signal associated with a first value or a signal associated with a second value in the read operation, based on drain currents of the first and second transistors
Data Source
AI summary
There are disposed second and third transistors whose gates are connected to each other, and first and fourth transistors whose gates are connected to each other. Sources of the first to fourth transistors are connected to each other. A read operation is performed in a state where drain current is supplied to the fourth transistor, and drain current larger than that of the fourth transistor is supplied to the third transistor. In the read operation, a signal associated with a first or second value is output based on drain currents of the first and second transistors.