Non-Volatile Memory Overdrive Zoning for Read Margin Control

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Solution Overview

Problem

Non-volatile memory systems face challenges in maintaining reliable data read operations due to the narrowing margin between the erased state and the lowest programmed data state, which can lead to read disturb issues and increased failure bit count when using suboptimal overdrive voltages.

Innovation Solution

Implementing a method to adjust the overdrive voltage applied to unselected word lines by identifying specific word lines that require a lower neighbor overdrive voltage, thereby reducing the narrowing margin issue without increasing failure bit count.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a standard overdrive voltage is applied to all unselected word lines, then the read operation is simple to implement, but the margin between erased state and lowest programmed data state narrows leading to read disturb and increased failure bit count

Engineering Contradiction:
Improvemargin between erased state and lowest programmed data stateVSAvoidoverdrive voltage application complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies different overdrive voltage levels to different groups of unselected word lines based on their position relative to the selected word line. Specifically, a first overdrive voltage is applied to unselected word lines in a first group, and a second overdrive voltage is applied to unselected word lines in a second group, where the groups are defined by their proximity to the selected word line. This local differentiation maintains sufficient margins between data states while enabling accurate read operations.

Inventive Principle:
Principle #3Local quality

2Reliability

If a lower neighbor overdrive voltage is applied to specific word lines, then the narrowing margin issue is reduced, but the overdrive voltage control becomes more complex

Engineering Contradiction:
Improvefailure bit countVSAvoidoverdrive voltage control
Core Design Contradiction:
ReliabilityVSEase of operation

Solution Approach 1:

The patent segments the unselected word lines into multiple groups based on their position relative to the selected word line. The first group receives a first overdrive voltage while the second group receives a second overdrive voltage. This segmentation allows the system to apply optimized voltage levels to specific word line groups, reducing the narrowing margin issue and failure bit count while maintaining manageable control through systematic grouping.

Inventive Principle:
Principle #1Segmentation

3Reliability

If uniform overdrive voltage is used across all unselected word lines, then the voltage control is simple, but read disturb increases due to insufficient margin maintenance

Engineering Contradiction:
Improveread disturbVSAvoidvoltage zoning structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent implements voltage zoning by applying different overdrive voltage levels to different groups of unselected word lines. The first group of unselected word lines receives a first overdrive voltage, while the second group receives a second overdrive voltage. This local quality approach ensures that each group receives the appropriate voltage level to maintain sufficient margins and prevent read disturb, while the systematic grouping keeps the voltage zoning structure manageable.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS12400719B2Non-volatile memory with overdrive voltage zoning to compensate for reduced margins
Publication Date: 2025.08.26 SANDISK TECHNOLOGIES LLC
  • US12400719B2 patent drawing
  • US12400719B2 patent drawing
  • US12400719B2 patent drawing

AI summary

During a read operation for memory cells connected a selected word line, a memory system adjusts the overdrive voltage applied to word lines adjacent the selected word line in order to compensate for margin degradation between the erased data state and the lowest programmed data state.