Nonvolatile Memory Page Regions with Independent Source Lines
Solution Overview
Problem
Nonvolatile memory devices face challenges in reducing coupling capacitance between adjacent bit lines during programming operations and minimizing read disturbance and power consumption during reading operations, particularly in multi-page region configurations.
Innovation Solution
The implementation of bit-line switch circuits that operate independently, with isolation transistors and common source lines controlled separately for each page region, allows for reduced coupling capacitance and power consumption by precharging even bit lines while grounding odd bit lines during reading operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If bit lines are precharged during reading operations, then reading speed is improved, but coupling capacitance between adjacent bit lines increases
Solution Approach 1:
The memory array is divided into multiple independent page regions (first page region, second page region), each with its own dedicated common source line (first common source line, second common source line). This segmentation allows selective activation of only the page region being accessed, isolating the precharging activity to specific bit line groups and reducing capacitive coupling effects across the entire array.
Solution Approach 2:
Different voltage conditions are applied to different page regions simultaneously. When reading from the first page region, the first common source line is connected to ground while the second common source line is connected to power supply voltage, creating localized electrical conditions that minimize interference and coupling capacitance between adjacent bit lines in the active region.
2Productivity
If all common source lines are activated during reading, then reading coverage is improved, but power consumption increases
Solution Approach 1:
The system dynamically controls the connection state of each common source line based on the active page region. Control logic selectively connects the relevant common source line to ground while connecting others to power supply voltage, enabling adaptive power management that maintains full reading coverage capability while minimizing instantaneous power consumption through selective activation.
3Area of stationary object
If bit-line switch circuits are integrated for each page region, then integration density is improved, but device complexity increases
Solution Approach 1:
The bit-line switch circuits are designed with multi-functional capability to operate independently across multiple page regions. Each switch circuit can selectively connect to different common source lines and control different bit line groups, allowing a single switch circuit design to serve multiple functions and page regions, thereby improving integration density without proportionally increasing overall device complexity.
Data Source
AI summary
A nonvolatile memory device includes a memory cell array having multiple memory cells arranged at intersections of word lines and bit lines, a first page region configured with at least two adjacent memory cells coupled to a word line, and a second page region configured with at least two adjacent memory cells coupled to the word line. The nonvolatile memory devices also includes a first common source line connecting with the memory cells of the first page region, and a second common source line connecting with the memory cells of the second page region. The first and second common source lines are controlled independently.