Non-volatile Memory Partial Planes for RC Delay Reduction
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Solution Overview
Problem
As memory devices scale down, resistive/capacitive (RC) delays on word lines become a limiting factor in performance, leading to slowed writing and reading due to worst-case scenario parameters, which are not optimized for localized areas, resulting in inefficient data access in smaller units.
Innovation Solution
The implementation of a non-volatile memory system with partial planes allows for localized optimization of writing and reading parameters, enabling partial page operations with optimized pulse algorithms to minimize RC delays, allowing for faster and more efficient data access in smaller units.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory devices scale down to increase storage density, then storage capacity is improved, but RC delays on word lines increase causing slower writing and reading
Solution Approach 1:
The memory array is divided into multiple segments along the word line direction, with each segment serving as an independent access unit. This segmentation allows partial page operations to be performed on smaller subsets of memory cells, reducing the RC delay impact and enabling faster access times while maintaining high storage density through continued scaling.
2Reliability
If worst-case scenario parameters are used for writing and reading, then reliability is improved, but performance is degraded due to non-optimized localized areas
Solution Approach 1:
Different operational parameters are applied to different segments of the memory array based on their specific characteristics. Each segment can be independently optimized for its local RC delay characteristics, allowing reliable operation while maximizing performance. This local quality approach enables partial page operations with optimized timing and voltage parameters tailored to each segment's physical properties.
Data Source
AI summary
A non-volatile memory system comprises a memory structure and a control circuit connected to the memory structure. The memory structure includes one or more planes of non-volatile memory cells. Each plane is divided into a plurality of partial planes. The control circuit is configured to write to and read from the memory cells by writing a partial page into a particular partial plane and reading the partial page from the particular partial plane using a set of parameters optimized for the particular partial plane.