Non-Volatile Memory Pin Multiplexing for Efficient Idle-Time Data Transfer
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Solution Overview
Problem
The inefficiency of data transmission between non-volatile memory devices and controllers in storage devices, particularly due to the inability to transmit data while commands or addresses are being transmitted, reduces the overall input/output efficiency of the interface.
Innovation Solution
A memory system design that allows for the transmission of data through the same pins used for commands and addresses during idle times, utilizing a first pin for command and address transmission and a second pin for data transmission, with error correction and parity bits generated during these idle periods.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data transmission is performed only through dedicated data pins while commands and addresses are transmitted through separate pins, then signal integrity is maintained, but input/output efficiency decreases due to inability to transmit data during command transmission
Solution Approach 1:
The first pin is designed to serve multiple functions: transmitting commands and addresses during active periods, and transmitting data during idle periods. This multi-functional approach allows the same physical pin to be reused for different communication purposes at different times, thereby improving I/O efficiency without requiring additional dedicated pins for each function.
Solution Approach 2:
The pin's functional role dynamically changes based on the communication phase. During command transmission phases, the first pin operates as a command/address channel; during idle periods between commands, the same pin dynamically switches to function as a data transmission channel. This dynamic reconfiguration optimizes resource utilization.
2Loss of time
If multiple pins are used for simultaneous command and data transmission, then transmission parallelism is achieved, but pin usage increases and interface complexity increases
Solution Approach 1:
The patent merges the command transmission function and data transmission function into a single pin (the first pin). By combining these functions temporally rather than spatially, the system achieves efficient communication without requiring separate dedicated pins for each function, thus reducing the total pin count while maintaining transmission efficiency.
Solution Approach 2:
Instead of adding more pins in the spatial dimension to achieve parallel transmission, the patent utilizes the temporal dimension by transmitting data during idle periods between commands. This dimensional shift from spatial parallelism to temporal multiplexing reduces pin requirements while maintaining effective transmission throughput.
3Productivity
If data is transmitted during idle time between commands, then I/O efficiency improves, but timing synchronization complexity increases
Solution Approach 1:
The system uses feedback mechanisms where the controller monitors the completion status of commands and identifies idle periods. Based on this feedback, the controller determines when to transmit data through the first pin, ensuring proper timing synchronization. The memory device also provides feedback signals to confirm data reception, enabling coordinated timing between controller and memory device.
Solution Approach 2:
The communication follows a periodic pattern where commands are transmitted at regular intervals, creating predictable idle periods between command sequences. This periodic structure allows the system to rhythmically switch between command transmission mode and data transmission mode on the first pin, simplifying timing control through regular, predictable cycles rather than irregular timing events.
Data Source
AI summary
A non-volatile memory device, a controller, and a memory system are provided. The non-volatile memory device includes a first pin configured to receive a command and an address from a controller and to communicate first data with the controller, a memory cell array including a plurality of memory cells, and control logic configured to control an operation on the plurality of memory cells based on the command and the address, wherein the first data is communicated through the first pin during an idle time, wherein the idle time starts when the command and the address are received through the first pin and ends after the first data is communicated through the first pin.