Nonvolatile Memory Programming Method Using Segmented Verification
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Solution Overview
Problem
Existing nonvolatile memory devices face challenges in achieving a fine threshold voltage distribution for multi-level flash memory devices, leading to read errors and reduced data storage reliability, particularly when storing multiple bits in each memory cell.
Innovation Solution
A method is introduced that involves applying program voltages and verification voltages in a controlled manner to selected memory cells, adjusting bit line voltages, and using pre-verification and target verification voltages to program memory cells from a first set of logic states to a second set, ensuring a fine threshold voltage distribution and improved programming speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are programmed to have multiple logic states for storing multiple bits per cell, then data storage capacity increases, but threshold voltage distribution becomes coarse leading to read errors
Solution Approach 1:
The programming process is divided into multiple stages with different verification voltages. The method segments the verification process into first verification (using first verification voltage) and second verification (using second verification voltage), where each stage targets specific logic states. This segmentation allows precise control over threshold voltage distribution across multiple logic states, enabling fine threshold voltage distribution while maintaining multi-level cell functionality.
Solution Approach 2:
The method applies preliminary programming voltages to transition memory cells between logic states before final verification. By pre-programming cells to intermediate logic states and verifying them with appropriate verification voltages, the system ensures that threshold voltages are precisely positioned within target ranges before completing the programming operation, thus achieving fine threshold voltage distribution.
2Manufacturing precision
If verification voltages are applied to all logic states, then programming accuracy improves, but programming speed decreases
Solution Approach 1:
The verification process is segmented into different stages with different verification voltages applied at different times. The first verification voltage is applied during initial programming stages, and the second verification voltage is applied in later stages. This segmentation allows the system to maintain high programming accuracy while avoiding the need to apply all verification voltages simultaneously, thus preserving programming speed.
Solution Approach 2:
The method performs preliminary verification using the first verification voltage before applying the second verification voltage. This preliminary action allows the system to identify and correct programming errors early in the process, reducing the need for repeated programming cycles and ultimately improving both accuracy and speed.
3Manufacturing precision
If bit line voltage is adjusted during programming, then fine threshold voltage distribution is achieved, but device complexity increases
Solution Approach 1:
The bit line voltage is dynamically adjusted during the programming process based on the current programming stage and target logic state. The control circuit modifies bit line voltage levels in response to verification results and programming progress, enabling fine threshold voltage distribution without requiring complex additional hardware. The dynamic adjustment is achieved through programmable voltage generators that can adapt their output based on control signals.
Data Source
AI summary
A method of programming memory cells (transistors) of a nonvolatile memory device from a first set of (previous) logic states to a second set of (final) logic states. The method includes applying program voltages to selected memory transistors; and applying a pre-verification voltage and a target verification voltage for verifying the current logic state of the selected memory transistors. The voltage interval between logic states of the second set of logic states is less than the voltage interval between logic states of the first set of logic states. A target verification voltage for verifying a first memory transistor is at one logic state of the second set is used as a pre-verification voltage for verifying that a second memory transistor to be programmed to higher logic state of the second set.