Nonvolatile Memory Device With Segmented Word Lines
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Solution Overview
Problem
Three-dimensional NAND flash memory devices face increased word line loading and reduced read performance due to shared word line structures, leading to longer setup times and decreased performance.
Innovation Solution
The nonvolatile memory device incorporates a selection line driver with path transistors that isolate and provide distinct operation voltages to string selection and ground selection transistors, reducing word line loading by separating local and global ground selection lines and applying specific bias voltages to selected and unselected memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If shared word line structure is used in three-dimensional NAND flash memory, then device complexity is reduced, but word line loading increases and read performance deteriorates
Solution Approach 1:
The patent segments the previously shared word line into multiple independent word lines (first word line and second word line), each dedicated to specific NAND strings. This segmentation reduces the loading on each individual word line, thereby improving read performance while maintaining manageable device complexity through systematic organization.
Solution Approach 2:
The patent applies local quality by providing different voltage conditions to different regions. Specifically, selected NAND strings receive appropriate read voltages on their dedicated word lines, while unselected NAND strings have their word lines floating or held at specific potentials, optimizing read performance for active cells without affecting inactive ones.
2Ease of manufacture
If shared word line structure is used, then manufacturing is simplified, but word line setup time increases
Solution Approach 1:
By dividing the word line into separate segments (first word line for first NAND strings, second word line for second NAND strings), the patent enables independent voltage setup for each segment. This reduces the time required to prepare word lines for reading operations, as each segment can be charged independently rather than waiting for a shared line to service multiple strings.
Solution Approach 2:
The patent implements preliminary action by pre-charging or floating the word lines of unselected NAND strings before the actual read operation begins. This preliminary voltage setup prevents capacitive coupling effects during reading, reducing setup time and improving overall operation speed.
3Device complexity
If ground selection lines are not separated, then device complexity is reduced, but capacitance in unselected NAND strings increases
Solution Approach 1:
The patent segments the ground selection line structure into local ground selection lines (first and second local ground selection lines) that are selectively connected to different NAND string groups. This segmentation allows unselected NAND strings to have their local ground selection lines disconnected or floating, thereby reducing parasitic capacitance and improving read performance.
Solution Approach 2:
The patent applies local quality by providing different ground selection line configurations to different regions. Selected NAND strings have their local ground selection lines connected to establish proper reference potential, while unselected NAND strings have their local ground selection lines floating or connected to different potentials, reducing unwanted capacitive effects locally where needed.
4Device complexity
If string selection transistors are electrically connected through shared structures, then device complexity is reduced, but read performance deteriorates due to increased loading
Solution Approach 1:
The patent segments the string selection transistor connections by providing separate first string selection transistors connected to first NAND strings and separate second string selection transistors connected to second NAND strings. This segmentation isolates the selection paths, reducing cross-talk and loading effects, thereby improving read performance while maintaining systematic device organization.
Data Source
AI summary
According to example embodiments, a nonvolatile memory device includes a first and a second NAND string. The first NAND string includes a first string selection transistor, a first local ground and a first global ground selection transistor, and first memory cells stacked in a direction perpendicular to a substrate. The second NAND string includes a second string selection transistor, a second local ground and a second global ground selection transistor, and second memory cells stacked in the direction perpendicular to the substrate. The device includes a selection line driver including path transistors configured to select and provide at least one operation voltage to the first and second string selection transistors, the first and second local and global ground selection transistors. The first and second string selection transistors are electrically isolated from each other, and the first and second global ground selection transistors are electrically connected.