Nonvolatile Memory Selective Erase via Hole Injection
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Solution Overview
Problem
Conventional flash memories face reliability degradation and decreased rewriting speed due to the need to rewrite memory cells that do not require data changes, and they struggle with selective erasure, which affects the lifetime and efficiency of memory cells.
Innovation Solution
A nonvolatile semiconductor memory device with a memory unit comprising multiple memory strings and select transistors, where a control unit applies specific voltages to selectively erase memory cells by injecting holes or extracting electrons, allowing only the necessary cells to be rewritten, thereby improving reliability and speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If collective erase operation is used to rewrite data, then all memory cells can be rewritten, but memory cells that do not need rewriting are also rewritten causing reliability degradation and decreased rewriting speed
Solution Approach 1:
The patent divides the memory array into multiple independently controllable memory strings, each with its own select transistors. This segmentation allows selective erasure of only the required memory cells by controlling specific select transistors, avoiding unnecessary rewriting of other cells and improving both reliability and rewriting speed
Solution Approach 2:
The patent applies different voltage conditions to different select transistors and their associated memory strings. By applying a first voltage to one select transistor and a second voltage (lower than the first) to another select transistor, the patent creates local differences in erasure conditions, enabling precise control over which memory cells undergo erasure while protecting others from unnecessary stress
2Ease of operation
If selective erasure is implemented using holes from band-to-band tunneling current, then local electric field is applied to memory cells, but reliability degrades due to the narrow driving margin between selected and non-selected cells
Solution Approach 1:
The patent changes the voltage parameters applied to select transistors to create a wider driving margin. By applying a first voltage to a selected cell's select transistor and a second voltage (lower than the first) to non-selected cells' select transistors, the patent ensures that only the selected cell undergoes erasure while non-selected cells remain protected, thereby improving operation stability and reliability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables selective and stable rewriting of memory cells, extending their lifetime and allowing for high-speed data rewriting, thereby enhancing the operational reliability and efficiency of the memory device.
Implementation Method 1
injection of a hole into a charge retention layer of a selected cell transistor in the selective erase operation
Implementation Method 2
extraction of an electron from the charge retention layer of the selected cell transistor in the selective erase operation
Data Source
AI summary
A nonvolatile semiconductor memory device includes: a memory unit; and a control unit. The memory unit includes: first and second memory strings including first and second memory transistors with first and second select gates, respectively; and first and second wirings connected thereto. In a selective erase operation of a selected cell transistor of the first memory transistors, the control unit applies V1 voltage to the first wiring, applies V2 voltage lower than V1 to a selected cell gate of the selected cell transistor, applies V3 voltage not higher than V1 and higher than V2 to a non-selected cell gate of the first memory transistors, applies V1 or V4 voltage not higher than V1 and not lower than V3 to the first select gate, and applies V2 or V4 voltage higher than V2 and not higher than V3 to the second wiring or sets the second wiring in a floating state.