Non-volatile Memory Sharp Tip Gate Structure
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Solution Overview
Problem
Non-volatile memory devices with a floating gate and select gate require higher voltages and larger overlapping regions for programming and erasing operations, limiting the miniaturization of memory cells.
Innovation Solution
A non-volatile memory structure is developed with a third conductive layer that covers a sharp tip of the first conductive layer, reducing the voltage needed for programming and erasing operations and minimizing the overlapping region, thereby allowing for smaller memory cell sizes. This structure includes a substrate, conductive layers, doped regions, and dielectric layers, with specific fabrication methods such as ion implantation and chemical mechanical polishing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a floating gate and select gate are used in non-volatile memory, then programming and erasing operations can be performed, but higher voltage and greater overlapping region are required, preventing further reduction of memory cell size
Solution Approach 1:
The gate structure is segmented into a first conductive layer (floating gate) and a second conductive layer (select gate) that are separated from each other. This segmentation allows the memory cell to perform programming and erasing operations through controlled charge injection and removal, while reducing the overlapping region between gates and thereby reducing the overall memory cell area.
Solution Approach 2:
The patent introduces a vertical dimension by stacking conductive layers and dielectric layers to form a three-dimensional structure. The first and second conductive layers are disposed at different vertical positions, allowing for reduced planar overlap while maintaining functional separation. This vertical arrangement enables smaller memory cell footprint without compromising programming and erasing capabilities.
2Reliability
If higher voltage is applied for programming and erasing operations, then data storage functionality is achieved, but energy consumption increases and device complexity increases
Solution Approach 1:
The patent applies local quality by creating distinct regions with different electrical characteristics. The first conductive layer and second conductive layer are separated and can be independently controlled, allowing for localized charge injection and removal. This enables programming and erasing operations to be performed with reduced voltage requirements compared to conventional split gate structures, as each layer can be optimized for its specific function without requiring high voltage across the entire gate structure.
Solution Approach 2:
The patent changes the electrical parameters by introducing a separated gate structure with specific dielectric layers between the first and second conductive layers. This structural modification alters the electric field distribution and charge injection characteristics, enabling programming and erasing operations at lower voltages while maintaining data retention capability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces the voltage and overlapping region required for programming and erasing, enabling further reduction in memory cell size without compromising performance.
Implementation Method 1
the erasing method of the non-volatile memory is, for instance, performing erasing between the first conductive layer and the third conductive layer via a Fowler-Nordheim (FN) tunneling method
Implementation Method 2
A first doped region is formed in the substrate at one side of the first conductive layer away from the second conductive layer. A second doped region is formed in the substrate at one side of the second conductive layer away from the first conductive layer.
Data Source
AI summary
A non-volatile memory including the following elements is provided. A first conductive layer and a second conductive layer are disposed on a substrate and separated from each other. A patterned hard mask layer is disposed on the first conductive layer and exposes a sharp tip of the first conductive layer. A third conductive layer is disposed on the substrate at one side of the first conductive layer away from the second conductive layer. The third conductive layer is located on a portion of the first conductive layer and covers the sharp tip, and the third conductive layer and the first conductive layer are isolated from each other. A first doped region is disposed in the substrate below the third conductive layer. A second doped region is disposed in the substrate at one side of the second conductive layer away from the first conductive layer.