Nonvolatile Memory Slow Erase Detection via Dual Voltage Scan
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Solution Overview
Problem
In non-volatile memory storage systems, particularly in solid-state drives, the 'slow to erase' signature defect caused by structural defects like word line-to-memory hole shorts can lead to undetected threshold voltage distributions during erase verify operations, compromising data reliability and integrity.
Innovation Solution
A method involving an erase/verify memory operation with an alternating word line scheme, followed by a read/verify operation with a higher read-pass voltage, to detect and designate memory structures with a 'fail' status if the bit scan mode criteria are not satisfied, ensuring early detection of defective memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a standard erase verify operation is performed, then the memory structure can be quickly verified, but defective memory cells with 'slow to erase' signature cannot be detected
Solution Approach 1:
The patent applies preliminary action by performing an erase verify operation before the main read operation. This preliminary erase verify step prepares the memory structure by attempting to erase it, and then a subsequent read operation detects any residual threshold voltage that indicates a 'slow to erase' defect. This two-step preliminary detection approach identifies defective cells before they cause uncorrectable errors during normal operation.
Solution Approach 2:
The patent utilizes parameter changes by applying different voltage levels at different stages. Specifically, it uses an erase verify voltage level during the erase verify operation, then applies a read-pass voltage level during the subsequent read operation. The comparison of threshold voltage measurements under these different voltage conditions enables detection of the 'slow to erase' signature that would be invisible under standard single-voltage verification.
2Reliability
If a read operation with higher read-pass voltage is applied, then 'slow to erase' signatures can be detected, but the operation time increases
Solution Approach 1:
The patent applies partial action by performing a limited additional read operation only on memory structures that failed the initial erase verify check. Rather than applying the more time-consuming read-pass voltage to all memory structures, the method selectively applies it only to those showing signs of potential defects, thus reducing overall time loss while maintaining high detection capability for 'slow to erase' signatures.
3Ease of operation
If alternating word line scheme is used during erase verify, then the detection process is simplified, but some defective cells may be missed
Solution Approach 1:
The patent implements feedback by using the results of the initial erase verify operation to determine whether to proceed with the additional read operation. If the erase verify operation indicates potential issues (failure to meet verification criteria), the system feedbacks this information and triggers the subsequent read operation with read-pass voltage. This feedback mechanism ensures that alternating word line simplification does not compromise detection coverage, as suspicious cells are re-examined with the more sensitive read operation.
Data Source
AI summary
A method for detecting a “slow to erase” condition of a non-volatile memory structure, wherein the method comprises initiating an erase/verify memory operation with respect to the memory structure, wherein the erase/verify memory operation comprises applying an erase verify voltage according to an alternating word line scheme; following the erase/verify memory operation, determining if a first bit scan mode criteria is satisfied; and, if the first bit scan mode criteria is satisfied, initiating a read/verify memory operation wherein, the read/verify memory operation comprises applying a read-pass voltage according to an all word line scheme, and a magnitude of the read-pass voltage is greater than a magnitude of the erase verify voltage. Following the read/verify memory operation, the method also comprises determining if a second bit scan mode criteria is satisfied and, if the criteria is not satisfied, designating the memory structure with a fail status.