Nonvolatile Memory Read Operation Voltage Slope Control

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Solution Overview

Problem

As semiconductor memory devices are scaled down for higher integration and capacity, they face issues with reliability, operating speed, and increased peak current, which affect the performance and efficiency of nonvolatile memory devices.

Innovation Solution

An operation method for nonvolatile memory devices that adjusts the balance between reliability, operating speed, and peak current by varying the voltage slope applied to unselected word lines during the setup phase, including pre-pulse and read pass voltages, to optimize the read operation and reduce peak current.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If the storage device is scaled down due to high degree of integration, then manufacturing cost is reduced, but peak current increases and reliability deteriorates

Engineering Contradiction:
Improvemanufacturing costVSAvoiddevice reliability
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The patent applies preliminary action by applying a pre-pulse voltage to unselected word lines before the main read voltage is applied. This pre-conditioning step prepares the memory cells in advance, preventing interference effects that would otherwise compromise read accuracy in scaled-down devices with higher density and closer cell spacing.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent changes voltage parameters by introducing a multi-stage voltage application scheme: first applying a pre-pulse voltage (e.g., 3V) to unselected word lines, then transitioning to a read pass voltage (e.g., 4V). This parameter transformation allows the device to maintain reliability in scaled-down configurations by dynamically adjusting voltage levels to compensate for reduced cell spacing and increased interference.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If new technologies for securing reliability are applied, then reliability is improved, but operating speed decreases and peak current increases

Engineering Contradiction:
Improvedevice reliabilityVSAvoidoperating speed
Core Design Contradiction:
ReliabilityVSSpeed

Solution Approach 1:

The patent segments the voltage application process into distinct phases: a first setup phase where pre-pulse voltage is applied to unselected word lines, and a second setup phase where read pass voltage is applied. This temporal segmentation allows reliability measures to be implemented without unnecessarily extending the total read operation time, as each phase has a specific function that can be optimized independently.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent employs dynamic voltage adjustment by varying the voltage level applied to unselected word lines based on the operational phase. During the first setup phase, a lower pre-pulse voltage is applied, and during the second setup phase, a higher read pass voltage is applied. This dynamic approach optimizes both reliability and speed by applying voltage only when and where needed, rather than maintaining high voltage throughout the entire operation.

Inventive Principle:
Principle #15Dynamics

3Reliability

If new technologies for securing reliability are applied, then reliability is improved, but peak current increases

Engineering Contradiction:
Improvedevice reliabilityVSAvoidpeak current
Core Design Contradiction:
ReliabilityVSPower

Solution Approach 1:

The patent applies partial action by selectively applying pre-pulse voltage only to unselected word lines during the first setup phase, rather than applying voltage to all word lines. This selective approach provides the necessary reliability protection for unselected cells while minimizing the overall current consumption, as fewer transistor gates are activated simultaneously compared to a full-voltage application scheme.

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentUS11532365B2Operation method of nonvolatile memory device
Publication Date: 2022.12.20 SAMSUNG ELECTRONICS CO LTD
  • US11532365B2 patent drawing
  • US11532365B2 patent drawing
  • US11532365B2 patent drawing

AI summary

An operation method of a nonvolatile memory device includes receiving a read command and an address, increasing a voltage applied to an unselected word line from an off voltage to a read pass voltage during a setup phase in response to the read command, increasing a voltage applied to an unselected string selection line from the off voltage to a pre-pulse voltage during a first setup phase of the setup phase, increasing a voltage applied to an unselected ground selection line from the off voltage to the pre-pulse voltage during the first setup phase, applying a read voltage to a selected word line to read data corresponding to the address, during a sensing phase following the setup phase, and outputting the read data through data lines after the sensing phase. During the setup phase, a slope of the voltage applied to the unselected word line is varied.