NOR Flash Floating Gate Etching Yield Improvement
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Solution Overview
Problem
The manufacturing process of NOR Flash devices with sizes of 0.13 μm or less results in poor yield due to the formation of isotropic openings in the floating gate, leading to charge leakage and device failure, primarily caused by impurity sources like Ni diffusing into the polycrystalline silicon layer and forming metal silicide during high-temperature processes.
Innovation Solution
Cleaning the gas pipeline connected to the etching cavity, especially the CO gas pipeline, before etching the first hard mask layer to prevent impurity sources like Ni from contaminating the polycrystalline silicon layer, ensuring anisotropic dry etching results and improving the formation of the floating gate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the distance between adjacent float gates is reduced to decrease storage region area, then the area efficiency is improved, but the manufacturing yield deteriorates due to isotropic etching and charge leakage
Solution Approach 1:
The patent changes the etching process parameters by introducing a gas pipeline cleaning step before etching the first hard mask layer. This cleaning step removes impurities (particularly Ni) from the etching cavity, which prevents the formation of metal silicide during subsequent high-temperature processes. As a result, the etching process transitions from producing isotropic openings to producing anisotropic openings, resolving the yield issue while maintaining the reduced gate spacing for area efficiency.
2Ease of manufacture
If impurity sources like Ni are present in the etching cavity, then the etching process can proceed, but metal silicide forms during high-temperature processes causing isotropic etching and device failure
Solution Approach 1:
The patent applies a preliminary cleaning action to the gas pipeline and etching cavity before the etching process begins. This preliminary cleaning removes impurity sources (particularly Ni) that would otherwise diffuse into the polycrystalline silicon layer during high-temperature processes. By performing this cleaning step in advance, the patent prevents the formation of metal silicide and ensures anisotropic etching, thereby maintaining device functionality while allowing the etching process to proceed.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method enhances the yield of NOR Flash devices by ensuring the floating gate meets the required anisotropic structure, reducing charge leakage and increasing the manufacturing success rate.
Implementation Method 1
etching the first hard mask layer to form a first opening using a dry etching process
Implementation Method 2
cleaning a gas pipeline connected to an etching cavity prior to etching the first hard mask layer
Implementation Method 3
etching the second hard mask layer to form a second opening using a self-aligning process
Data Source
AI summary
An embodiment of a NOR Flash device manufacturing method includes: providing a substrate having a first polycrystalline silicon layer disposed thereon; forming a first hard mask layer on the first polycrystalline silicon layer; etching the first hard mask layer to form a first opening, and cleaning a gas pipeline connected to an etching cavity before etching the first hard mask layer; forming a second hard mask layer on the first hard mask layer, and the second hard mask layer covers the bottom and side wall of the first opening; etching the second hard mask layer to form a second opening, the width of the second opening is smaller than the width of the first opening; etching the first polycrystalline silicon, forming a floating gate. The NOR Flash device manufacturing method improves the yield of the NOR Flash device.