Multi-Level Cell NOR Flash Memory Parasitic Capacitance Reduction
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Solution Overview
Problem
NOR flash memory devices face reduced performance due to non-uniform distribution of critical voltage caused by parasitic capacitance, leading to decreased transconductance and conforming rate.
Innovation Solution
A multi-level cell NOR flash memory device with a metal silicide layer on gate lines, source and drain regions, and a specific layout of bitlines and power lines, along with a soft-programming procedure, to enhance transconductance and uniformity among memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If flash memory reading/programming process is performed, then data access is achieved, but parasitic capacitance is generated causing non-uniform voltage distribution
Solution Approach 1:
The patent applies local quality by introducing a metal silicide layer specifically on the gate lines to reduce parasitic capacitance in critical areas. This localized modification improves voltage distribution uniformity without changing the overall memory architecture, allowing fast access while maintaining voltage uniformity across memory cells.
Solution Approach 2:
The patent changes the physical parameter of the gate line by using metal silicide material instead of conventional metal, which has different electrical properties (lower parasitic capacitance). This parameter change directly addresses the voltage distribution issue while preserving the high-speed access capability.
2Quantity of substance
If memory density is increased by switching to multi-level cells, then storage capacity is improved, but voltage uniformity and performance are degraded
Solution Approach 1:
The metal silicide layer is applied locally on gate lines in the multi-level cell structure, providing targeted parasitic capacitance reduction in the critical voltage distribution paths. This allows the multi-level cell architecture to maintain high storage capacity while improving voltage uniformity through localized material optimization.
3Reliability
If parasitic capacitance is reduced through metal silicide layer, then transconductance is improved, but device complexity increases
Solution Approach 1:
The patent merges the gate line structure with a metal silicide layer, combining the conductive function with the parasitic capacitance reduction function in a single integrated structure. This approach improves transconductance and reliability without significantly increasing device complexity, as the metal silicide layer is formed as part of the existing gate line fabrication process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution achieves high transconductance, uniformity, and improved electrical performance, resulting in enhanced capacity, speed, and stability of the NOR flash memory device.
Implementation Method 1
the reading/programming process of flash memory is accompanied by generation of parasitic capacitance that inevitably decreases the applied voltage from the very beginning
Implementation Method 2
a plurality of gate lines separated from a semiconductor substrate by a gate insulating layer
Data Source
AI summary
A multi-level cell NOR flash memory device includes a plurality of gate lines, a plurality of source regions, a plurality of drain regions, a plurality of source lines, a plurality of bitlines, and a plurality of power lines. The bitlines each have a specific sheet resistance. A specific number of the bitlines are disposed between two adjacent ones of the power lines. Accordingly, the multi-level cell NOR flash memory device is of a high transconductance and uniformity and thereby features an enhanced conforming rate.