NOR Hybrid Multi-Bit Memory Cell Structure
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Solution Overview
Problem
Current non-volatile memory (NVM) devices face limitations in increasing memory integrity and speed due to constraints in processing technology for fabricating fine patterns, which restricts their ability to enhance data processing and storage capabilities, especially in mobile devices like phones and digital cameras.
Innovation Solution
The development of NOR-type hybrid multi-bit non-volatile memory devices with a hybrid structure, comprising unit cells that include a channel, a first memory unit with a charge storage node and a second memory unit with a variable resistance node, connected by a switch, allowing for dual operating systems and improved data storage and retrieval methods.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional NVM devices use single-structure memory cells, then manufacturing is simpler, but memory capacity and speed are limited
Solution Approach 1:
The patent combines two different memory structures (first memory unit with charge storage node and second memory unit with resistance storage node) into a single hybrid memory cell. This merging allows the device to leverage the advantages of both memory types - the high density of charge storage and the fast read speed of resistance storage - thereby increasing overall memory capacity and speed while managing complexity through integrated design
Solution Approach 2:
The hybrid memory cell is designed to perform multiple functions within a single structure: it can store data using threshold voltage changes in the first memory unit, store data using resistance changes in the second memory unit, and share common control mechanisms (word lines, bit lines, source, drain). This multi-functionality increases memory capacity and operational versatility without proportionally increasing device complexity
2Manufacturing precision
If processing technology is advanced to fabricate finer patterns, then memory integrity and speed improve, but manufacturing difficulty increases
Solution Approach 1:
The patent divides the memory cell into distinct functional segments: a first memory unit with charge storage node for data storage, a second memory unit with resistance storage node for data storage, and shared control elements (word lines, bit lines, source, drain). This segmentation allows each component to be optimized independently for fine pattern fabrication while simplifying the overall manufacturing process through modular assembly
Solution Approach 2:
Different regions of the memory cell are designed with locally optimized properties: the first memory unit uses charge storage mechanisms suitable for high-density storage, while the second memory unit uses resistance storage for fast access. This local quality differentiation allows each region to be manufactured with appropriate precision levels, improving overall manufacturing feasibility while achieving high memory integrity and speed
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances memory capacity and speed by enabling efficient data storage and retrieval through the combination of threshold voltage transition and resistance varying mechanisms, thereby overcoming the limitations of existing NVM devices.
Implementation Method 1
The first storage node may include a first storage node capable of storing charges, and may read data according to variations or changes in a threshold voltage of the channel
Implementation Method 2
Related art NVM devices may be one of threshold voltage transition devices
Implementation Method 3
The second memory unit may include a second storage node having a resistance characteristic that vary according to an applied voltage
Data Source
AI summary
A hybrid multi-bit memory device may include a plurality of unit cells arranged in a matrix of a plurality of rows and columns. Each of the unit cells may include a first memory unit and a second memory unit. The first and second memory unit may share a source and a drain. The first memory unit of each unit cell arranged in each row may be connected to one of a plurality of word lines, and the drain of each unit cell arranged in each column may be connected to one of a plurality of bit lines.