NOR ROM Layout Grouping for Bit Line Loading Control
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Solution Overview
Problem
Existing integrated circuit (IC) designs face challenges in reducing cell size and improving circuit speed and power efficiency due to bit line loading issues, particularly in NOR-type ROM ICs, where conventional approaches fail to effectively control via density and programming complexity.
Innovation Solution
The IC layout is redesigned by dividing NOR-type ROM bit cells into groups of more than two cells separated by isolation features, assigning logic patterns to each group, and further dividing these groups into units, with logic patterns defined to include both 0-bit and 1-bit configurations, allowing for controlled via density and simplified programming.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If NOR-type ROM bit cells are grouped into groups of more than two cells separated by isolation features, then cell size is reduced and circuit speed is improved, but via density control and programming complexity increase
Solution Approach 1:
The patent divides the ROM bit cell array into multiple groups, where each group contains more than two bit cells separated by isolation features. This segmentation reduces the effective cell size by allowing shared resources (such as bit lines and word lines) across multiple cells within a group, thereby reducing the area required per bit while maintaining electrical isolation between groups through the isolation features.
Solution Approach 2:
The patent implements a universal programming pattern that can be applied across all groups of bit cells. By defining a standardized logic pattern that works for groups of more than two cells, the same programming approach and fabrication process can be used throughout the entire ROM array, reducing overall programming complexity despite the increased group size. The isolation features serve multiple functions: electrical isolation, physical separation, and programming boundary definition.
2Use of energy by moving object
If logic patterns are assigned to groups of more than two bit cells, then bit line loading is reduced and power efficiency improves, but manufacturing precision requirements increase
Solution Approach 1:
By segmenting the bit cell array into groups separated by isolation features, the patent reduces the number of active bit lines that need to be driven simultaneously. Each group can be programmed and accessed independently, reducing the capacitive loading on individual bit lines and thereby improving power efficiency during read and write operations.
Solution Approach 2:
The patent changes the via density parameter within each group by strategically placing vias to connect the shared bit lines and word lines to the bit cells. The isolation features create natural boundaries that allow for optimized via placement patterns, reducing overall via density while maintaining precise electrical connections. This parameter optimization reduces manufacturing complexity and improves power efficiency simultaneously.
3Speed
If groups of bit cells are separated by isolation features, then circuit speed is improved, but device area increases
Solution Approach 1:
The patent segments the ROM array into multiple groups separated by isolation features, which improves circuit speed by reducing the capacitive loading on bit lines and allowing for shorter signal paths within each group. The isolation features act as electrical barriers that prevent signal interference between adjacent groups, enabling faster switching and read operations.
Solution Approach 2:
The patent utilizes the two-dimensional layout space efficiently by arranging bit cells and isolation features in a grid pattern. The isolation features are positioned at strategic locations that minimize their area impact while maximizing their electrical isolation effectiveness. By optimizing the dimensional arrangement of cells, isolation features, and interconnect lines, the patent achieves fast circuit performance without proportionally increasing the overall device area.
Data Source
AI summary
A method of generating an IC layout diagram includes dividing a column of NOR-type read-only memory (ROM) bit cells into a plurality of N-bit groups separated by isolation features, wherein each group includes the number of bits N greater than two, based on a ROM code programming pattern of the column, assigning one or more logic patterns to each N-bit group of the plurality of N-bit groups, and storing an IC layout diagram including the logic patterns in a storage device.