North Bridge State Machine for Graphics Data Buffer Monitoring

Solution Overview

Problem

In computer systems with a chipset, display interruptions occur due to insufficient graphics data in the north bridge buffer, leading to lengthy CPU state switching and power consumption issues, especially in graphic integrated chipsets with complex inner circuits and limited data storage.

Innovation Solution

A state machine within the north bridge monitors graphics data and sends an NB control signal to the CPU to access system memory directly, allowing continuous graphics data access without switching CPU power states, using an NB control signal to enable an embedded memory controller and maintain data flow.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If the CPU switches from deep power saving state C3 to shallower state C0 to access system memory for graphics data, then sufficient graphics data can be acquired, but the switching time is long and causes display interruption

Engineering Contradiction:

Improvegraphics data quantityVSAvoidCPU state switching time

Core Design Contradiction:

Quantity of substanceVSLoss of time

Solution Approach 1:

The north bridge performs preliminary actions by monitoring the graphics data buffer level and proactively sending the LDTSTOP_NB# signal to the CPU before the buffer is completely empty. This allows the CPU to be notified in advance and switch power states timely, preventing display interruption while avoiding unnecessarily early wake-ups.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The north bridge implements a feedback mechanism by continuously monitoring the graphics data buffer level and dynamically controlling the LDTSTOP_NB# signal based on the buffer status. When the buffer level is sufficient, the CPU remains in deep power saving state; when the buffer level drops below the threshold, the north bridge sends the signal to wake the CPU, creating a closed-loop control system that optimizes power consumption and display continuity.

Inventive Principle:

Principle #23Feedback

2Use of energy by moving object

If the CPU remains in deep power saving state C3, then power consumption is reduced, but the north bridge buffer cannot be replenished causing display interruption

Engineering Contradiction:

ImproveCPU power consumptionVSAvoiddisplay continuity

Core Design Contradiction:

Use of energy by moving objectVSReliability

Solution Approach 1:

The north bridge implements a feedback mechanism by continuously monitoring the graphics data buffer level and dynamically controlling the LDTSTOP_NB# signal based on the buffer status. When the buffer level is sufficient, the CPU remains in deep power saving state; when the buffer level drops below the threshold, the north bridge sends the signal to wake the CPU, creating a closed-loop control system that optimizes power consumption and display continuity.

Inventive Principle:

Principle #23Feedback

Solution Approach 2:

The north bridge performs preliminary actions by monitoring the graphics data buffer level and proactively sending the LDTSTOP_NB# signal to the CPU before the buffer is completely empty. This allows the CPU to be notified in advance and switch power states timely, preventing display interruption while avoiding unnecessarily early wake-ups.

Inventive Principle:

Principle #10Preliminary action

3Reliability

If the north bridge buffer size is increased to store more graphics data, then display continuity is maintained during CPU power state switching, but the chipset complexity and area increase

Engineering Contradiction:

Improvedisplay continuityVSAvoidchipset structure

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The LDTSTOP_NB# signal acts as an intermediary communication mechanism between the north bridge and CPU. Instead of increasing buffer size, the north bridge uses this control signal to coordinate with the CPU, requesting wake-up only when necessary. This intermediary approach enables reliable display continuity through efficient inter-component communication rather than through hardware expansion.

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The invention changes the operational parameters of the system by introducing a threshold-based buffer level monitoring mechanism. Instead of relying on large buffer capacity, the system changes to a dynamic parameter approach where the north bridge monitors buffer levels and triggers CPU wake-up based on predefined thresholds, achieving display continuity through parameter optimization rather than hardware scaling.

Inventive Principle:

Principle #35Parameter changes

Data Source

PatentUS7457972B2South and north bridge and related computer system for supporting CPU

Publication Date: 2008.11.25 VIA TECH INC

AI summary

A circuit, designed for supporting a computer system having a CPU, a monitor, and a system memory electrically connected to the CPU, includes a south bridge, and a north bridge electrically connected to the south bridge, the CPU, and the monitor. The north bridge includes a state machine and a graphics data buffer. When detecting that graphics data transferred by the graphics data buffer to the monitor is insufficient, the state machine sends a north bridge signal to the CPU to access inner data of the system memory.