Notched Common Gate Line for ESD Protection in TFT Arrays
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Solution Overview
Problem
The fabrication of thin film transistor array substrates is hindered by electrostatic discharge effects that cause line shorts and reduce electrical quality and reliability, as static electricity accumulates and leads to damage in the dielectric layer, particularly between terminals and the common gate line.
Innovation Solution
The design incorporates notches on the edge of the common gate line, with drain electrodes extending from the top of the common gate line to the notches and then to the terminals of the signal lines, reducing the distance for electrostatic discharge and preventing short circuits, while also optimizing the layout to minimize space usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the distance between terminals and common gate line is increased to prevent electrostatic discharge effects, then reliability is improved, but area of stationary object increases
Solution Approach 1:
The common gate line is segmented into multiple sections by forming notches that divide it into first, second, third, and fourth sections. This segmentation allows the drain electrode to connect to different sections at different distances, preventing direct long-distance electrostatic discharge paths while maintaining electrical connectivity through multiple shorter paths.
Solution Approach 2:
The drain electrode is designed with a three-dimensional structure that extends in multiple directions - vertically from the channel layer and horizontally to connect to different sections of the common gate line. This multi-dimensional configuration reduces the effective electrostatic discharge distance in any single direction while maintaining compact substrate usage.
2Reliability
If notches are formed on the common gate line to reduce electrostatic discharge distance, then reliability is improved, but device complexity increases
Solution Approach 1:
The common gate line is divided into multiple sections by notches, creating a segmented structure that breaks up continuous electrostatic discharge paths. This segmentation approach prevents direct long-distance discharge while maintaining the gate line's primary function with minimal additional complexity.
Solution Approach 2:
The notched common gate line structure serves multiple functions simultaneously: it maintains the gate line's electrical connectivity for transistor operation, provides segmented paths to reduce electrostatic discharge effects, and enables the drain electrode to connect to multiple sections for enhanced reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design effectively prevents electrostatic discharge-induced defects, enhancing the electrical properties and process yield of the thin film transistor array substrate by reducing the likelihood of short circuits and improving substrate utilization.
Implementation Method 1
static electricity is usually accumulated in the terminals 132a and the common gate line 142 to cause electrostatic discharge effects (ESD effects)
Data Source
AI summary
A thin film transistor array substrate includes a substrate having a display area and a peripheral area, a plurality of pixel units, a plurality of signal lines, and a testing circuit. The signal lines are electrically connected with the pixel units disposed in the display area. The testing circuit disposed in the peripheral area is electrically connected with terminals, located in the peripheral area, of a portion of the signal lines. The testing circuit includes a common gate line having a plurality of notches formed on an edge thereof, a plurality of channel layers, source electrodes, and drain electrodes. The source electrodes and the drain electrodes are disposed correspondingly on the channel layers disposed above the common gate line. Each drain electrode extends from the top of the common gate line to the top of one notch and extends to the terminal of one signal line for electrically connecting thereto.