Notched Gate Structure for Power MOS Transistors
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Solution Overview
Problem
Power MOS transistor devices, such as LDMOS, are susceptible to snapback and the Kirk effect, which can lead to device damage due to secondary charge carrier generation and voltage shifts, limiting their safe operating area and requiring increased device size or resistance to prevent damage.
Innovation Solution
The implementation of a notched gate structure in semiconductor devices, which suppresses the Kirk effect and delays snapback by creating a low resistivity path for secondary charge carriers and increasing channel resistance, thereby maintaining or expanding the safe operating area without significant increases in on-resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional gate structure is used in power MOS transistor devices, then the device can operate with lower on-resistance, but the device is susceptible to snapback and Kirk effect which limit the safe operating area
Solution Approach 1:
The gate structure is segmented by introducing notches that divide the gate into multiple sections. These notches create distinct regions that allow secondary charge carriers to be extracted through dedicated paths, preventing their accumulation that would otherwise cause snapback and Kirk effect. The segmentation enables localized control of charge carrier behavior without affecting the entire gate structure.
Solution Approach 2:
The notched gate structure extracts secondary charge carriers (holes) from the drift region through the notches, removing them before they can accumulate and trigger snapback or Kirk effect. This extraction mechanism actively removes harmful charge carriers from the critical regions where they would cause damage.
2Reliability
If device size is increased to prevent snapback and Kirk effect, then the safe operating area is protected, but the on-resistance increases significantly
Solution Approach 1:
The notched gate structure applies local quality changes by concentrating protective features (notches) at specific locations where secondary charge carrier extraction is most needed, rather than uniformly increasing the entire device size. This allows protection against snapback in critical regions while maintaining lower on-resistance in the overall device structure.
3Loss of energy
If channel length is reduced to lower on-resistance, then power loss is reduced, but the device becomes more susceptible to snapback and Kirk effect
Solution Approach 1:
The notched gate structure introduces asymmetry into the gate design, creating non-uniform regions that provide enhanced protection against snapback specifically in areas where secondary charge carriers are generated, while allowing the channel length to be reduced for lower on-resistance. The asymmetric notch placement optimizes protection without requiring symmetric increases in device dimensions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The notched gate structure effectively increases the safe operating area of power MOS transistor devices, reducing the risk of snapback and Kirk effect-induced damage while maintaining relatively low on-resistance, even with reduced channel lengths.
Implementation Method 1
The notched gates may be used to address the generation of secondary charge carriers in power transistor devices
Implementation Method 2
increasing channel resistance, thereby maintaining or expanding the safe operating area without significant increases in on-resistance
Implementation Method 3
Power devices are susceptible to the generation of secondary charge carriers through impact ionization. In an n-channel LDMOS transistor device, electrons may generate additional electron-hole pairs after being accelerated in a region having a high electric field
Data Source
AI summary
A semiconductor device includes a semiconductor substrate, a body region disposed in the semiconductor substrate and having a first conductivity type, a source region disposed in the semiconductor substrate adjacent the body region and having a second conductivity type, a drain region disposed in the semiconductor substrate, having the second conductivity type, and spaced from the source region to define a conduction path, a gate structure supported by the semiconductor substrate, configured to control formation of a channel in the conduction path during operation, and having a side adjacent the source region that comprises a notch, the notch defining a notch area, and a notch region disposed in the semiconductor substrate in the notch area and having the first conductivity type.