Notched Wafer Support Structure for Uniform 3D Bonding

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Solution Overview

Problem

The challenge in manufacturing 3D integrated circuits (ICs) arises from non-bond regions (NB regions) due to non-planar surfaces on semiconductor wafers, leading to issues like chipping, cracking, and reduced structural integrity during wafer stacking and thinning processes.

Innovation Solution

A method involving a semiconductor wafer with a notch and a bonding support structure, where an upper and lower plasma exclusion zone (PEZ) rings are used to align and deposit the support structure continuously along the notch, reducing step height differences and mitigating NB regions, thereby enhancing structural integrity and yield.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Strength

If a bonding support structure is formed over the peripheral region of a semiconductor wafer, then structural integrity during bonding is improved, but non-bond regions and step height issues occur due to uneven deposition

Engineering Contradiction:

Improvestructural integrityVSAvoiddeposition uniformity

Core Design Contradiction:

StrengthVSManufacturing precision

Solution Approach 1:

The bonding support structure is segmented into two distinct regions: a first bonding support structure formed over the central region and a second bonding support structure formed over the peripheral region. This segmentation allows each region to be optimized independently, with the peripheral region providing enhanced structural support while the central region maintains deposition uniformity, thereby resolving the contradiction between structural integrity and deposition uniformity.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Different regions of the bonding support structure are given different properties: the peripheral region (second bonding support structure) is designed with higher structural support characteristics to prevent wafer deformation, while the central region (first bonding support structure) is optimized for uniform material deposition. This local differentiation resolves the contradiction by providing strength where needed without compromising overall deposition uniformity.

Inventive Principle:

Principle #3Local quality

2Productivity

If the minimum feature size is shrunk to improve processing capabilities, then processing capabilities and power consumption are improved, but process limitations make it difficult to continue shrinking

Engineering Contradiction:

Improveprocessing capabilitiesVSAvoidprocess limitations

Core Design Contradiction:

ProductivityVSEase of manufacture

Solution Approach 1:

The patent transitions from two-dimensional planar integration to three-dimensional vertical stacking of semiconductor wafers. By stacking multiple wafers vertically, the system achieves continued improvement in processing capabilities and power consumption without further shrinking the minimum feature size in the lateral dimension, thereby overcoming the process limitations that constrain further feature size reduction.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

3Productivity

If wafer stacking is implemented to improve processing capabilities, then three-dimensional integration is achieved, but non-bond regions reduce bonding reliability

Engineering Contradiction:

Improveprocessing capabilitiesVSAvoidbonding reliability

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The bonding interface is segmented into central and peripheral bonding support structures with different functional optimizations. The peripheral bonding support structure specifically addresses bonding reliability by providing enhanced support and preventing non-bond regions, while enabling the overall wafer stacking architecture that delivers improved processing capabilities through three-dimensional integration.

Inventive Principle:

Principle #1Segmentation

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach reduces step height issues, minimizes damage during thinning processes, and increases the structural integrity and reliability of 3D ICs by ensuring continuous deposition of the bonding support structure, thus improving the bonding process and overall IC performance.

Implementation Method 1

upper and lower plasma exclusion zone (PEZ) ring, where the lower PEZ ring has a notch aligned with the wafer notch, ensuring continuous deposition along the notch

Methodology Applied

Scientific EffectPlasma exclusion zone: Plasma

Data Source

PatentUS12622303B2Notched wafer and bonding support structure to improve wafer stacking

Publication Date: 2026.05.05 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

Various embodiments of the present disclosure are directed towards a processing tool. The processing tool includes a housing structure defining a chamber. A first plate is disposed in the chamber. A first plasma exclusion zone (PEZ) ring is disposed on the first plate. A second plate is disposed in the chamber and underlies the first plate. A second PEZ ring is disposed on the second plate. The second PEZ ring comprises a PEZ ring notch that extends inwardly from a circumferential edge of the second PEZ ring.