NPU Clock Frequency Control for Power Stability
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Neural processing units (NPUs) face challenges in stabilizing supply voltage and reducing power consumption due to fluctuating computational demands across layers of artificial neural network models, leading to potential system instability and increased power usage.
Innovation Solution
A system that includes a neural processing unit with a switching circuit capable of selecting clock signals with different frequencies based on the utilization rate of processing elements across layers, stabilizing the supply voltage and reducing power consumption by adjusting the clock frequency according to the computational load.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the number of processing elements in the neural processing unit is increased to improve parallel processing performance, then the processing speed is improved, but the supply voltage fluctuates or drops instantaneously due to excessive power consumption
Solution Approach 1:
The patent applies dynamics by making the clock frequency adjustable rather than fixed. The neural processing unit dynamically changes clock frequency based on the computational load of different layers, allowing the system to adapt its power consumption and processing speed to match actual requirements, thereby preventing voltage fluctuations while maintaining high productivity when needed
Solution Approach 2:
The patent changes the clock frequency parameter according to the computational demands of different neural network layers. By adjusting this key parameter, the system can reduce power consumption during low-computation layers to prevent voltage drops, while maintaining high frequency during high-computation layers to ensure processing performance
2Speed
If the clock frequency is increased to improve processing speed, then the processing speed is improved, but the power consumption increases causing supply voltage to drop
Solution Approach 1:
The system dynamically adjusts clock frequency based on the computational load characteristics of each layer. During layers with low computational requirements, the clock frequency is reduced to lower power consumption and prevent voltage drops. During layers with high computational requirements, the clock frequency is increased to maintain processing speed, thus dynamically balancing speed and energy usage
Solution Approach 2:
The patent implements periodic adjustment of clock frequency corresponding to the periodic processing of different neural network layers. The clock frequency is modulated periodically according to the computational intensity of each layer being processed, creating a rhythm of high and low power states that matches the computational workload pattern
3Reliability
If the clock frequency is decreased to reduce power consumption and stabilize supply voltage, then the power consumption is reduced and voltage stability is improved, but the processing speed is lowered
Solution Approach 1:
The patent changes the clock frequency parameter adaptively based on the computational load of each layer. Rather than maintaining a constantly low frequency, the system adjusts the frequency parameter upward during high-computation layers to preserve processing speed, and downward during low-computation layers to stabilize voltage, thus resolving the contradiction between voltage stability and productivity
Data Source
AI summary
A system may comprise a neural processing unit (NPU) including a plurality of processing elements (PEs) capable of performing computations for at least one artificial neural network (ANN) model; and a switching circuit. The switching circuit may be configured to select one clock signal among a plurality of clock signals having different frequencies, and supply the selected clock signal to the NPU. The one clock signal may be selected based on a utilization rate of the plurality of PEs for a particular layer among a plurality of layers of the at least one ANN model.