N-SADP Process for Even-Numbered Word Lines
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Solution Overview
Problem
The conventional negative self-aligned double patterning (N-SADP) process in semiconductor technology is unable to produce an even number of equally-spaced word lines in a memory block, which is necessary for current memory standards.
Innovation Solution
An improved N-SADP process that involves forming patterned small and large core bodies on a substrate, depositing a spacer material layer, filling the recesses with specific materials, and performing multiple etching processes to pattern the hard mask and conductive layers, allowing for the creation of an even number of equally-spaced word lines by transforming odd-numbered patterns into even-numbered configurations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional negative self-aligned double patterning (N-SADP) process is used, then fine circuit patterns with intervals smaller than 28 nm can be produced, but the number of word lines in a single memory block is definitely an odd number which cannot fulfill current memory standards requiring even number of word lines
Solution Approach 1:
The patent divides the memory block into multiple unit structures, each containing core bodies and spacers. By controlling the number and arrangement of core bodies in each unit, the process can produce either odd or even numbers of word lines depending on the specific memory standard requirements, thus resolving the contradiction between achieving fine pitch and complying with even-number word line standards.
Solution Approach 2:
The patent introduces different types of core bodies (first core bodies and second core bodies) with different properties into different regions of the memory block. This allows local variation in word line formation, enabling the overall even number requirement to be met while maintaining fine pitch characteristics in specific critical regions.
2Manufacturing precision
If double patterning technology is adopted to achieve finer circuit patterns, then current photolithographic tools can be used without expensive advanced tools, but the process complexity increases with multiple patterning steps
Solution Approach 1:
The patent performs preliminary patterning of core bodies before forming spacers. By pre-positioning the core bodies in specific arrangements, the subsequent spacer formation process automatically generates the desired even number of word lines through self-aligned lateral growth, reducing the need for additional complex patterning steps.
Solution Approach 2:
The spacer material layer forms word lines through self-aligned lateral growth from the core bodies. This self-service mechanism automatically ensures proper alignment and spacing without requiring additional alignment steps or complex process control, simplifying the overall double patterning process while maintaining fine pitch accuracy.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This process effectively produces an even number of equally-spaced word lines and select gates, addressing the limitation of the conventional N-SADP process and enhancing memory capacity by ensuring compliance with current memory standards.
Implementation Method 1
forming a spacer material layer conformally on the substrate and the core body groups
Data Source
AI summary
A semiconductor circuit structure and process of making the same is provided in the present invention, comprising the steps of providing a substrate having a target layer and a hard mask layer, forming a patterned small core body group and a large core body group on the hard mask layer, forming a spacer material layer conformally on the substrate and the core body groups, forming filling bodies in each recess of the spacer material layer, performing a first etching process to remove exposed spacer material layer, using the filling bodies as a mask to perform a second etching process for patterning the hard mask layer, and using the patterned hard mask layer as a mask to perform a third etching process for patterning the conductive layer.