NSFET Inner Spacer Structure for Low Capacitance Isolation
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Solution Overview
Problem
As semiconductor devices continue to shrink in size, the challenge of reducing parasitic capacitance and preventing electrical shorts between source/drain regions and the gate structure becomes critical, particularly in nanostructure field-effect transistors (NSFETs).
Innovation Solution
A multi-layer spacer film is formed with a first dielectric layer having a higher dielectric constant and a second dielectric layer with lower etch resistance, which is then annealed to fill sidewall recesses and trimmed to form inner spacers, achieving a balance between dielectric constant and etch resistance, thereby reducing parasitic capacitance and preventing electrical shorts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single-layer dielectric material is used to fill sidewall recesses, then the manufacturing process is simple, but it cannot simultaneously achieve low parasitic capacitance and high etch resistance
Solution Approach 1:
The spacer structure is segmented into multiple layers: a first dielectric layer (SiN) providing etch resistance, a second dielectric layer (SiOC) providing low-k properties, and a third dielectric layer (SiN) providing additional etch resistance. This segmentation allows each layer to perform its specialized function, resolving the contradiction between etch resistance and parasitic capacitance reduction
Solution Approach 2:
The invention uses a composite multi-layer dielectric structure combining materials with different properties (SiN for etch resistance, SiOC for low-k). This composite approach enables the spacer to simultaneously achieve high etch resistance from the SiN layers and low parasitic capacitance from the SiOC layer, resolving the technical contradiction
2Reliability
If a multi-layer spacer film is formed to balance dielectric constant and etch resistance, then parasitic capacitance is reduced and electrical shorts are prevented, but the manufacturing process complexity increases
Solution Approach 1:
The multi-layer spacer film is formed preliminarily before source/drain region formation, establishing the etch resistance barrier and low-k structure in advance. This preliminary action prevents electrical shorts and controls parasitic capacitance before subsequent processing steps, resolving the contradiction between reliability improvement and process complexity
Solution Approach 2:
The invention changes the dielectric constant parameter by incorporating low-k SiOC material in the second layer, while maintaining etch resistance through SiN layers. This parameter optimization allows simultaneous achievement of low parasitic capacitance and high etch resistance, addressing the technical contradiction
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces parasitic capacitance and ensures high etch resistance, preventing electrical shorts and enhancing the performance of nanostructure field-effect transistors (NSFETs) in advanced processing nodes.
Implementation Method 1
after depositing the second dielectric material, the second dielectric material is annealed
Data Source
AI summary
A method of forming a semiconductor device includes: forming a dummy gate structure over a fin structure that protrudes above a substrate, where the fin structure includes a fin and a layer stack over the fin, where the layer stack comprises alternating layers of a first semiconductor material and a second semiconductor material; forming openings in the fin structure on opposing sides of the dummy gate structure, where the openings exposes first portions of the first semiconductor material and second portions of the second semiconductor material; recessing the exposed first portions of the first semiconductor material to form sidewall recesses in the first semiconductor material; lining the sidewall recesses with a first dielectric material; depositing a second dielectric material in the sidewall recesses on the first dielectric material; after depositing the second dielectric material, annealing the second dielectric material; and after the annealing, forming source/drain regions in the openings.