Non-Volatile Memory Cell Capacitor Structure Surrounding Active Region
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Solution Overview
Problem
Conventional non-volatile memory (NVM) cells face challenges in increasing capacitive coupling between the control gate electrode and the charge storage layer without significantly increasing the substrate area occupied by the NVM cell, with coupling ratios typically below 0.75 for existing designs like FinFET NVM cells.
Innovation Solution
A non-volatile memory cell design featuring a capacitor structure that surrounds the active region, with a floating gate electrode and a control gate electrode, where the capacitor structure includes multiple capacitor portions with specific electrical connections, and a process for forming the cell involving multiple layers and etch masks to optimize capacitive coupling without increasing the cell's area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the control gate electrode is extended to laterally surround the floating gate electrode (FETMOS design), then the capacitive coupling ratio is improved (approximately 0.6), but the substrate area occupied by the NVM cell increases
Solution Approach 1:
The patent transitions from planar 2D electrode arrangements to a 3D vertical structure where the control gate electrode wraps around the floating gate electrode in multiple dimensions. This vertical stacking and lateral surrounding configuration increases capacitive coupling surface area without proportionally increasing the substrate footprint, achieving higher coupling ratios while maintaining compact cell area.
Solution Approach 2:
The control gate electrode is configured to laterally surround and partially enclose the floating gate electrode, creating a nested configuration where one electrode structure contains another. This nested arrangement maximizes the capacitive coupling interface between gates while minimizing the overall lateral space required, directly addressing the area-coupling ratio tradeoff.
2Reliability
If the FinFET NVM cell structure is used, then the coupling ratio is improved (higher than 0.7 but less than 0.75), but further improvement without significant area increase is difficult
Solution Approach 1:
The control gate electrode is divided into multiple segments or portions that are positioned at different locations around the floating gate electrode. These segmented gate portions work together to provide enhanced capacitive coupling while allowing independent optimization of each segment's position and size, achieving superior coupling ratios without excessive complexity.
Data Source
AI summary
A non-volatile memory cell can include a substrate, an active region overlying the substrate, and a capacitor structure overlying the substrate. From a plan view, the capacitor structure surrounds the active region. In one embodiment, the non-volatile memory cell includes a floating gate electrode and a control gate electrode. The capacitor structure comprises a first capacitor portion, and the first capacitor portion comprises a first capacitor electrode and a second capacitor electrode. The first capacitor electrode is electrically connected to the floating gate electrode, and the second capacitor electrode is electrically connected to the control gate electrode. A process for forming the non-volatile memory cell can include forming an active region over a substrate, and forming a capacitor structure over the substrate, wherein from a plan view, the capacitor structure surrounds the active region.