Single-Transistor NVM Cell Back-Gate Select Gate Design
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Solution Overview
Problem
Conventional non-volatile memory (NVM) cells require two transistors for each memory cell, leading to larger chip sizes and higher costs due to increased feature size, and they struggle with issues like over-erase cell disturb and random dopant fluctuation.
Innovation Solution
A single-transistor NVM cell design using a thin silicon-on-insulator (SOI) substrate with a front-gate as the control gate and a back-gate embedded in the substrate as the select gate, eliminating the need for a separate select gate and reducing chip size while maintaining performance benefits like high mobility and low random dopant fluctuation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If two transistors are used for each memory cell, then select gate functionality is achieved, but chip area increases and manufacturing complexity increases
Solution Approach 1:
The patent merges the select gate functionality into the substrate by forming a back-gate structure that is shared across multiple memory cells. Instead of requiring separate select transistors for each cell, the back-gate embedded in the substrate provides selective access to multiple cells simultaneously, reducing the overall transistor count and chip area while maintaining the essential select gate functionality.
Solution Approach 2:
The back-gate structure serves multiple functions: it acts as a select gate for multiple memory cells, provides substrate bias control, and enables channel formation. This multi-functional design eliminates the need for separate dedicated select transistors for each memory cell, thereby reducing chip area and manufacturing complexity while maintaining reliable selective access.
2Reliability
If two transistors are used for each memory cell, then select gate functionality is achieved, but device complexity increases
Solution Approach 1:
The patent merges the select gate functionality into the substrate by forming a back-gate structure that is shared across multiple memory cells. Instead of requiring separate select transistors for each cell, the back-gate embedded in the substrate provides selective access to multiple cells simultaneously, reducing the overall transistor count and chip area while maintaining the essential select gate functionality.
Solution Approach 2:
The back-gate structure serves multiple functions: it acts as a select gate for multiple memory cells, provides substrate bias control, and enables channel formation. This multi-functional design eliminates the need for separate dedicated select transistors for each memory cell, thereby reducing chip area and manufacturing complexity while maintaining reliable selective access.
3Reliability
If conventional SONOS structure is used, then charge storage capability is achieved, but over-erase cell disturb issues occur
Solution Approach 1:
The patent introduces an interfacial layer between the silicon nitride charge storage layer and the silicon substrate. This interfacial layer acts as a mediator that prevents direct interaction between the trapped charges and the substrate, thereby reducing the harmful over-erase effect and cell disturb issues while preserving the charge storage capability of the silicon nitride layer.
Solution Approach 2:
The patent modifies the conventional SONOS structure by changing the physical and chemical parameters of the interface between the charge storage layer and substrate. By introducing an interfacial layer with specific properties, the patent alters the electric field distribution and charge trapping characteristics, thereby reducing over-erase effects while maintaining effective charge storage.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The single-transistor NVM cell achieves compactness, reduced chip area requirements, simplified manufacturing processes, and improved performance with enhanced control over the channel, leading to better leakage management and faster operation.
Implementation Method 1
a second gate embedded in the substrate which functions as a select gate
Implementation Method 2
The single transistor includes a first gate on the substrate which functions as a control gate and a second gate embedded in the substrate which functions as a select gate
Data Source
AI summary
A memory device and a method of making the same are presented. The memory device includes a substrate and a memory cell formed on the substrate. The memory cell includes a single transistor. The single transistor includes a first gate on the substrate which functions as a control gate and a second gate embedded in the substrate which functions as a select gate.