3D Non-Volatile Memory Charge Blocking Layer Thickness Compensation
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Solution Overview
Problem
The challenge in fabricating 3D NVM devices is the non-uniformity of memory cell characteristics due to angled channel holes, which affects the electric field distribution and integration density, leading to deteriorated performance and increased process complexity as the stacked structure height increases.
Innovation Solution
A method involving the formation of a stacked structure with interlayer insulating and gate electrode layers, channel pillar formation, and a trimming and oxidation process to create a charge blocking layer with varying thicknesses, ensuring uniformity and improving the integration density by compensating for angular channel hole shapes through oxidation of sacrificial layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If channel holes are formed with angled portions to increase integration density, then the degree of integration increases, but the uniformity of memory cell characteristics deteriorates
Solution Approach 1:
The charge blocking layer is designed with non-uniform thickness, having a first thickness in the first region and a second thickness in the second region. This local variation compensates for the angled portions of the channel holes, ensuring uniform electric field distribution and consistent memory cell characteristics across different regions while maintaining high integration density.
Solution Approach 2:
The thickness parameter of the charge blocking layer is deliberately changed across different regions. By forming the charge blocking layer with different thicknesses (first thickness and second thickness) in different regions, the patent compensates for the geometric variations in channel holes, achieving uniform memory cell performance despite the angled hole structures.
2Quantity of substance
If the stacked structure height is increased to improve memory capacity, then the storage capacity increases, but the process complexity and fabrication difficulty increase
Solution Approach 1:
The charge blocking layer is segmented into different thickness regions (first region with first thickness, second region with second thickness) to address the challenges of fabricating tall stacked structures. This segmentation allows for compensated uniformity in memory cell characteristics even when the overall structure height is increased for higher capacity.
Solution Approach 2:
The charge blocking layer is formed with predetermined non-uniform thickness profile before subsequent fabrication steps. This preliminary action of creating thickness variation compensates for the angled channel hole portions early in the process, preventing uniformity issues from propagating through subsequent fabrication steps of the tall stacked structure.
3Ease of manufacture
If the charge blocking layer has uniform thickness, then the manufacturing process is simple, but the electric field distribution becomes non-uniform due to angled channel holes
Solution Approach 1:
Rather than maintaining uniform thickness throughout, the charge blocking layer is designed with local quality variations - different thicknesses in different regions. This local non-uniformity precisely compensates for the angled portions of channel holes, ensuring uniform electric field distribution and reliable memory cell operation.
Solution Approach 2:
The thickness parameter of the charge blocking layer is changed across different regions to match the geometric variations in the channel holes. By forming the layer with a first thickness in the first region and a second thickness in the second region, the patent achieves uniform electric field distribution despite the complexity introduced by angled channel holes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the uniformity and performance of memory cells by eliminating angled portions in the charge blocking layer, improving operating characteristics, and increasing the degree of integration without complicating the fabrication process.
Implementation Method 1
oxidizing a whole of the trimmed second material layer to form at least a portion of a charge blocking layer
Implementation Method 2
The trimming is performed using a wet chemical
Data Source
AI summary
A method for fabricating the three dimensional (3D), non-volatile memory (NVM) device includes: forming a stacked structure including a plurality of interlayer insulating layers and a plurality of first material layers which are alternately stacked; forming at least one channel hole penetrating through the stack structure; forming a second material layer along the at least one channel hole; trimming a surface of the second material layer; oxidizing a whole of the trimmed second material layer to form at least a portion of a charge blocking layer; and forming a charge storage layer and a tunnel insulating layer over the charge blocking layer.