NVM Programming with ECC for Slow-to-Program Bit Handling
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Solution Overview
Problem
Non-volatile memory systems face challenges with slow-to-program bits that can lead to product failure due to weak memory cells, which are difficult to detect until they become problematic, causing unexpected failures in integrated circuits.
Innovation Solution
The integration of an error correction code (ECC) system within non-volatile memory systems that uses normal and relaxed program verify voltage levels to assess and manage programming pulses, allowing ECC to correct single-bit errors during read operations and optimizing the programming process by determining when to rely on ECC for correction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional programming operations are used without ECC, then programming speed is maintained, but reliability deteriorates due to undetected weak memory cells causing product failure
Solution Approach 1:
The patent applies preliminary action by performing relaxed program verify operations during the programming process to identify slow-to-program bits before they become weak memory cells that could cause product failure. This early detection and classification of problematic bits prevents future failures without requiring complex post-manufacturing testing or repair systems.
Solution Approach 2:
The patent introduces an intermediary classification system that categorizes memory bits into different groups (normal, slow-to-program, weak) based on programming characteristics. This intermediary classification layer between the physical memory cells and the system logic enables reliable identification of problematic cells without adding complex external monitoring equipment.
2Manufacturing precision
If programming pulses are increased to ensure all bits program successfully, then programming completeness improves, but programming time increases due to slow-to-program bits requiring significantly more pulses
Solution Approach 1:
The patent segments the memory array into different classification groups (normal bits, slow-to-program bits, weak bits) based on their programming characteristics. This segmentation allows the system to apply different programming strategies to different segments, ensuring complete programming of all bits without forcing the entire array to wait for the slowest bits.
Solution Approach 2:
The patent applies partial action by providing sufficient programming pulses for normal bits while using ECC to handle the minority of slow-to-program bits that require additional pulses. This approach ensures programming completeness for all bits without unnecessarily extending the programming time for the majority of normal bits.
3Reliability
If weak memory cells are not detected early, then device complexity remains low, but reliability deteriorates as weak cells cause unexpected product failures
Solution Approach 1:
The patent performs preliminary detection of weak memory cells during the programming process itself, rather than relying on post-manufacturing testing. By classifying bits as slow-to-program or weak during programming, the system identifies problematic cells before they cause product failures in the field.
Solution Approach 2:
The patent implements feedback mechanisms through program verify operations that monitor the programming status of each bit and provide information about programming speed and success. This feedback enables real-time classification of memory cells and adjustment of programming strategies, making weak cell detection straightforward without complex external equipment.
Data Source
AI summary
A method of programming a non-volatile semiconductor memory device includes determining a number of bit cells that failed to program verify during a program operation. The bit cells are included in a subset of bit cells in an array of bit cells. The method further determines whether an Error Correction Code (ECC) correction has been previously performed for the subset of bit cells. The program operation is considered successful if the number of bit cells that failed to program verify after a predetermined number of program pulses is below a threshold number and the ECC correction has not been performed for the subset of bit cells.