Gate Dielectric Formation Process for Non-Volatile Memory Field Isolation Erosion
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Solution Overview
Problem
The integration of non-volatile memory (NVM) arrays into electronic devices is becoming increasingly difficult due to the multiple gate dielectric layers, which leads to field isolation region erosion and electrical shorts, as the corners of the substrate become exposed during etching, resulting in thinner gate dielectric layers and potential electrical failures.
Innovation Solution
A process is developed where field isolation regions are protected by forming as little as one gate dielectric layer within each region, with each gate dielectric layer having a targeted thickness, and exposing only a portion of the field isolation region to a single oxide etch, reducing erosion and electrical issues by minimizing exposure during gate dielectric formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple gate dielectric layers are formed through conventional etching processes, then non-volatile memory arrays can be integrated into electronic devices, but field isolation regions become eroded and corners of the substrate become exposed leading to thinner gate dielectric layers
Solution Approach 1:
The patent applies preliminary action by forming a protective layer over the field isolation regions before the etching process begins. This protective layer is formed in advance to prevent erosion of the field isolation regions during subsequent etching operations, thereby maintaining gate dielectric layer thickness uniformity at the substrate corners while enabling NVM array integration
Solution Approach 2:
The patent uses an intermediary protective layer that acts as a mediator between the etching process and the field isolation regions. This intermediate layer protects the field isolation regions from direct exposure to the etchant, preventing erosion and maintaining the integrity of the gate dielectric layers during the NVM integration process
2Device complexity
If field isolation regions are etched multiple times during gate dielectric layer formation, then multiple gate dielectric layers can be formed, but electrical shorts and leakage paths may form between transistors
Solution Approach 1:
The protective layer is formed preliminarily over the field isolation regions before any etching of gate dielectric layers occurs. This pre-formed protective layer prevents the field isolation regions from being etched away during subsequent processing steps, thereby maintaining electrical isolation between transistors while allowing multiple gate dielectric layers to be formed
Solution Approach 2:
The protective layer serves as an intermediary that allows the etching process to proceed for forming multiple gate dielectric layers without compromising the field isolation regions. This intermediate protective structure enables complex multi-layer gate dielectric formation while maintaining transistor electrical isolation
3Ease of manufacture
If the gate dielectric layer is thinner near the corner at field isolation regions, then the structure can be formed, but the gate dielectric layer may fail at voltages lower than the designed operating voltage
Solution Approach 1:
The protective layer is formed in advance over the field isolation regions before gate dielectric layer formation. This preliminary protection prevents excessive etching at the substrate corners, ensuring that the gate dielectric layer maintains adequate thickness and can withstand the designed operating voltage without premature breakdown
Solution Approach 2:
The protective layer provides beforehand cushioning or protection to the field isolation regions against etching damage. This prior protective measure compensates for the vulnerable corner regions, ensuring sufficient gate dielectric thickness is maintained to prevent breakdown at operating voltages
Data Source
AI summary
A process for forming an electronic device can be performed, such that as little as one gate electric layer may be formed within each region of the electronic device. In one embodiment, the electronic device can include an NVM array and other regions that have different gate dielectric layers. By protecting the field isolation regions within the NVM array and other regions while gate dielectric layer are formed, the field isolation regions may be exposed to as little as one oxide etch between the time any of the gate dielectric layers are formed the time such gate dielectric layers are covered by gate electrode layers. The process helps to reduce field isolation erosion and reduce problems associated therewith.