Non-Volatile Memory Gate Dielectric Thickness Optimization
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Solution Overview
Problem
In the deep sub-micron manufacturing process of semiconductor devices, non-volatile memory cells face challenges in achieving high integration and reduced size while maintaining good driving capability, as the thickness of gate dielectric layers affects the operating voltage and driving capability of transistors.
Innovation Solution
A method is proposed where the thickness of the gate dielectric layer of the select transistor is reduced by removing a portion of the first gate dielectric layer, forming a second gate dielectric layer with a thickness of 50 Å to 70 Å, and a third gate dielectric layer with a thickness of 15 Å to 40 Å for core transistors, using lithographic etching and thermal oxidation processes, respectively, to enhance driving capability and reduce operating voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the gate dielectric layer thickness is increased to withstand higher operating voltage, then the reliability is improved, but the driving capability is reduced
Solution Approach 1:
The patent applies different gate dielectric layer thicknesses to different transistor types within the same memory device. Specifically, the first gate dielectric layer has a first thickness for input/output transistors, while the second gate dielectric layer has a second thickness (greater than the first) for memory transistors. This local differentiation allows each transistor type to have optimized electrical characteristics suited to its specific functional requirements.
Solution Approach 2:
The patent changes the physical parameter of gate dielectric layer thickness to optimize transistor performance. By forming gate dielectric layers with different thicknesses (first thickness for I/O transistors, second thickness for memory transistors), the patent adjusts the electrical characteristics to balance reliability and driving capability across different functional blocks of the memory device.
2Power
If the gate dielectric layer thickness is decreased to improve driving capability, then the power is improved, but the reliability is reduced
Solution Approach 1:
The patent applies different gate dielectric layer thicknesses to different transistor types within the same memory device. Specifically, the first gate dielectric layer has a first thickness for input/output transistors, while the second gate dielectric layer has a second thickness (greater than the first) for memory transistors. This local differentiation allows each transistor type to have optimized electrical characteristics suited to its specific functional requirements.
Solution Approach 2:
The patent changes the physical parameter of gate dielectric layer thickness to optimize transistor performance. By forming gate dielectric layers with different thicknesses (first thickness for I/O transistors, second thickness for memory transistors), the patent adjusts the electrical characteristics to balance reliability and driving capability across different functional blocks of the memory device.
3Adaptability or versatility
If multiple polysilicon layers and dielectric layers are formed to create non-volatile memory cells, then the functionality is improved, but the device complexity is increased
Solution Approach 1:
The patent merges the manufacturing processes of CMOS logic devices and non-volatile memory cells into a single integrated process. By forming gate dielectric layers and gate electrodes that serve dual purposes for both I/O transistors and memory transistors, the patent reduces the total number of fabrication steps while maintaining the functionality of both device types.
Solution Approach 2:
The gate dielectric layers and gate electrodes formed in the patent serve multiple functions: they act as gate structures for both input/output transistors and memory transistors, and they provide voltage isolation between different transistor types. This multi-functionality reduces device complexity while maintaining full non-volatile memory functionality.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach increases the driving current and information guidance speed of memory units, allows for transistors with different gate dielectric layer thicknesses, and improves the quality and driving capability of core transistors, enabling higher integration and operation speed in non-volatile memory devices.
Implementation Method 1
A portion of the first gate dielectric layer on the select transistor region is removed, so as to form a second gate dielectric layer
Implementation Method 2
using lithographic etching and thermal oxidation processes, respectively
Data Source
AI summary
A method of manufacturing a non-volatile memory is provided. A substrate includes a memory cell region and a first periphery circuit region. The memory cell region includes a select transistor region. A first gate dielectric layer having a first thickness is formed on the substrate in the first periphery circuit region and the select transistor region. A portion of the first gate dielectric layer on the select transistor region is removed to form a second gate dielectric layer. The second dielectric layer has a second thickness, wherein the second thickness is less than the first thickness.