NVM Gate Replacement Layout for Planarization and Low Contact Resistance
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Solution Overview
Problem
The semiconductor industry faces challenges in reducing contact resistance and minimizing the number of lithography operations while manufacturing semiconductor devices with non-volatile memory cells and peripheral logic circuits, particularly due to height differences in interlayer dielectric layers between these areas, which affect chemical mechanical polishing and require additional processing steps.
Innovation Solution
A method is introduced where a substrate is etched to create a step between non-volatile memory cell and peripheral logic circuit areas before forming interlayer dielectric layers, allowing for the formation of isolation layers and planarization, and subsequently using metal material for control gates and gates in non-volatile memory cells to reduce resistance, while minimizing the number of lithography operations by performing gate replacement processes simultaneously for both areas.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a step is formed between NVM cell and peripheral logic circuit areas before fabrication, then the height difference in interlayer dielectric layers is compensated, but the manufacturing process complexity increases
Solution Approach 1:
A step is formed between the NVM cell area and peripheral logic circuit area before fabricating the gate structures and interlayer dielectric layers. This preliminary action compensates for the height difference in subsequent processing steps, enabling better planarity and reducing the number of additional lithography operations needed.
2Productivity
If the number of lithography operations is reduced, then manufacturing efficiency improves, but the manufacturing precision may be compromised
Solution Approach 1:
By forming the step structure in advance before gate and interlayer dielectric fabrication, the height difference is compensated early in the process. This allows subsequent lithography operations to proceed with fewer steps while maintaining alignment precision, as the step provides a stable reference structure.
3Reliability
If contact resistance is reduced, then device performance improves, but the manufacturing process becomes more complex
Solution Approach 1:
The step structure is formed before gate and interlayer dielectric fabrication to compensate for height differences. This preliminary action enables better contact formation and reduces contact resistance by ensuring proper planarity and alignment, while the overall process complexity is managed through this single preparatory step.
Data Source
AI summary
A semiconductor device includes a non-volatile memory. The non-volatile memory includes a first dielectric layer disposed on a substrate, a floating gate disposed on the dielectric layer, a control gate and a second dielectric layer disposed between the floating gate and the control gate. The second dielectric layer includes one of a silicon oxide layer, a silicon nitride layer, and a multi-layer thereof. The first dielectric layer includes a first-first dielectric layer formed on the substrate and a second-first dielectric layer formed on the first-first dielectric layer. The second-first dielectric layer includes a dielectric material having a dielectric constant higher than silicon nitride.