NVM Gate Stack Patterning with Dummy Etch Endpoint
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Solution Overview
Problem
The existing methods for patterning gate stacks in non-volatile memory (NVM) devices face challenges such as the need to minimize mask steps, achieving vertical sidewalls, and accurate end point detection, which are often compromised due to selectivity issues in etching processes, leading to over-etching and residual polymers.
Innovation Solution
The introduction of a sacrificial dummy gate stack in a separate region allows for simultaneous etching with the NVM gate stack, providing improved end point detection through additional endpoint material and potentially reducing the need for additional tiling features, thus enhancing the precision and efficiency of the etching process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If etchants with the best selectivity are used for gate stack etching, then selectivity is improved, but vertical sidewall quality deteriorates
Solution Approach 1:
The patent segments the etching process into multiple sequential etching steps rather than using a single etch. Each etching step uses different etchants optimized for specific layers, allowing selectivity to be maintained for each layer while achieving overall vertical sidewalls through the combination of steps
Solution Approach 2:
The patent applies preliminary patterning and protective layer formation before the main etching process. Photoresist patterns and protective layers are prepared in advance to guide the etching process and protect areas that should not be etched, enabling precise control of sidewall formation
2Manufacturing precision
If over etching is performed to ensure complete pattern transfer, then etching completeness is improved, but endpoint detection accuracy deteriorates and residual polymers increase
Solution Approach 1:
The patent implements real-time endpoint detection during the etching process using optical monitoring systems. The etching process is continuously monitored and automatically stopped when the predetermined endpoint is detected, providing feedback control that prevents over-etching while ensuring complete pattern transfer
Solution Approach 2:
The patent performs etching to a predetermined endpoint that is slightly before complete pattern transfer, relying on the protective layers and process design to ensure sufficient pattern definition without requiring excessive etching that would cause over-etching problems
3Measurement precision
If additional tiling features are created to provide endpoint material, then endpoint detection is improved, but device complexity and space requirements increase
Solution Approach 1:
The patent designs the gate stack structure itself to serve dual purposes: as the functional memory element and as the endpoint detection target. The same gate stack layers that form the NVM device also provide the material interfaces for endpoint detection, eliminating the need for separate tiling features
Solution Approach 2:
The patent uses the inherent material layers of the gate stack (such as the interface between different dielectric layers or conductive layers) as intermediary targets for endpoint detection. These existing layers serve as natural endpoints that provide sufficient optical contrast for detection without requiring additional sacrificial structures
Data Source
AI summary
Forming a gate stack of a non-volatile memory (NVM) over a substrate having an NVM region and non-NVM region which does not overlap the NVM region includes forming a select gate layer over the substrate in the NVM and non-NVM regions; simultaneously etching the select gate layer in the NVM and non-NVM regions; forming a charge storage layer over the substrate in the NVM and non-NVM regions; forming a control gate layer over the charge storage layer in the NVM and non-NVM regions; and simultaneously etching the charge storage layer in the NVM and the non-NVM regions. Etching the select gate layer in the NVM region results in a portion of the charge storage layer over a portion of the select gate layer and overlapping a sidewall of the select gate layer and results in a portion of the control gate layer over the portion of the charge storage layer.