NVM Logic Integration Using Multi-Layer Sacrificial Gate Patterning
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Solution Overview
Problem
The integration of Non-Volatile Memory (NVM) circuitry with logic circuitry in System-on-Chip (SoC) designs faces challenges due to the complexity of patterning small-dimensioned transistor gates, particularly with the use of thick anti-reflective coatings (BARC) which lead to non-planarity issues and inefficiencies in layout, as well as difficulties in etching regular anti-reflective coatings (ARC) in later processes.
Innovation Solution
The method employs multiple sacrificial layers, including an anti-reflective coating (ARC) layer, an etch stop layer, and a polishing stop layer, to pattern transistor gates in both NVM and logic areas, reducing the need for thick BARC layers and minimizing trench isolation size, thereby simplifying the integration process and optimizing space utilization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a thick BARC layer is deposited to achieve critical dimension control of gate dimensions, then the CD control is improved, but the process complexity increases and the layer becomes difficult to etch due to non-planarity
Solution Approach 1:
The patent segments the anti-reflective coating into multiple thinner layers (first ARC layer and second ARC layer) instead of using a single thick BARC layer. This segmentation allows each layer to be more easily deposited and etched while collectively providing the necessary critical dimension control for the transistor gates in both NVM and logic areas.
Solution Approach 2:
The patent applies different ARC layer configurations to different areas of the substrate. The first ARC layer is deposited over the entire substrate, while the second ARC layer is selectively deposited only in the logic area. This local quality approach optimizes the anti-reflective properties for each specific area's patterning needs without affecting other regions.
2Ease of manufacture
If the isolation region between memory area and logic area is increased to resolve non-planarity, then the non-planarity problem is reduced, but layout efficiency decreases
Solution Approach 1:
The patent segments the anti-reflective coating structure into multiple layers that can be independently processed, allowing for effective non-planarity management without requiring a large isolation region. The multi-layer ARC structure can be selectively etched to handle height differences between NVM and logic areas.
Solution Approach 2:
The patent addresses the non-planarity issue by adding a vertical dimension through multiple ARC layers rather than increasing the horizontal isolation region. The selective deposition and etching of the second ARC layer in the logic area allows for dimensional compensation without expanding the footprint.
3Manufacturing precision
If regular ARC or nitride is deposited for patterning small-dimensioned transistors, then the patterning capability is improved, but the etching difficulty increases due to non-planarity
Solution Approach 1:
The patent divides the anti-reflective coating into multiple thinner ARC layers instead of using a single thick layer of regular ARC or nitride. This segmentation makes each layer easier to etch while maintaining the patterning capability needed for small-dimensioned transistors in both NVM and logic areas.
Solution Approach 2:
The patent applies the second ARC layer selectively only in the logic area where small-dimensioned transistors are located. This local application provides the necessary patterning capability for logic transistors without creating etching difficulties across the entire substrate, as the ARC structure is optimized for each area's specific needs.
Data Source
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AI summary
A method for integrating Non-Volatile Memory (NVM) circuitry (18) with logic circuitry (20) is provided. The method includes depositing a first layer of gate material (16) over the NVM area and the logic area of a substrate (12). The method further includes depositing multiple adjoining sacrificial layers (22, 24, 26) comprising nitride, oxide and nitride (ARC layer) overlying each other. The multiple adjoining sacrificial layers (22, 24, 26) are used to pattern a select gate (16) and a control gate (32) of a memory transistor in the NVM area, and an ARC layer (22) of the multiple adjoining sacrificial layers (22, 24, 26) is used to pattern a gate (16) of a logic transistor in the logic area (20).