NVM Margin Read Stress Screening for Imminent Read Failure
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Solution Overview
Problem
Current error correcting code (ECC) technologies in non-volatile memory (NVM) systems cannot predict and prevent imminent read failures, which are critical in safety-critical applications like automotive systems, as they can only correct single-bit errors and not multiple-bit errors, leading to potential accidents.
Innovation Solution
Implementing a stress-based technique that applies a bulk high voltage read stress to the NVM array, followed by an array integrity check at a normal and then a margin read verify voltage level, using a combination of ECC and margin read circuits to detect imminent read failures by identifying uncorrectable errors at the margin read level.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional ECC is used to correct single-bit errors, then single-bit error correction is achieved, but multiple-bit errors and imminent read failures cannot be detected
Solution Approach 1:
The patent applies preliminary stress (bulk high voltage read stress) to the NVM array before actual read operations to accelerate degradation and induce imminent read failures. This preliminary action causes cells that are close to failing to actually fail, allowing the margin read circuit to detect them before they cause system errors. The stress is applied in advance to reveal potential failures that conventional ECC cannot predict.
Solution Approach 2:
The patent introduces a margin read circuit as an intermediary component between the NVM array and the ECC circuit. This margin read circuit performs reads at marginally lower verify voltage levels to detect cells that are close to failing but still pass normal reads. It acts as a mediator that identifies imminent failures before they become actual errors, providing early warning that conventional ECC alone cannot detect.
2Reliability
If bulk high voltage read stress is applied to accelerate failure detection, then imminent read failures are detected earlier, but additional circuit complexity and power consumption are introduced
Solution Approach 1:
The margin read circuit is designed to perform multiple functions: it can read at normal verify voltage levels for standard operations and at marginally lower verify voltage levels for imminent failure detection. The bulk high voltage read stress circuit can also serve dual purposes by accelerating degradation during diagnostic modes while potentially serving as a normal read circuit in other contexts. This multi-functionality reduces the need for completely separate dedicated failure detection hardware.
3Measurement precision
If margin read verify voltage level is used to detect imminent failures, then detection accuracy is improved, but read speed is reduced due to additional verification steps
Solution Approach 1:
The patent implements periodic stress and margin read operations rather than continuous operations. The bulk high voltage read stress is applied periodically to accelerate degradation, and margin reads are performed periodically to detect imminent failures. During normal operation between stress cycles, standard fast reads are used. This periodic approach balances detection accuracy with read speed by using the slower, more accurate margin reads only when necessary for failure detection.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively predicts and indicates imminent read failures, reducing the number of defective parts returned and ensuring safety by accelerating the detection of read failures in NVM systems, particularly in automotive applications.
Implementation Method 1
applying a bulk read stress... the bulk read stress applies a gate bias voltage (e.g., 6V), which is higher than the normal read voltage (e.g., 4.2V)
Data Source
AI summary
A technique for detecting an imminent read failure in a non-volatile memory array includes applying a bulk read stress to a plurality of cells of the non-volatile memory array and determining whether the plurality of cells exhibit an uncorrectable error correcting code (ECC) read during an array integrity check at a margin read verify voltage level subsequent to the bulk read stress. The technique also includes providing an indication of an imminent read failure for the plurality of cells when the plurality of cells exhibit the uncorrectable ECC read during the array integrity check. In this case, the margin read verify voltage level is different from a normal read verify voltage level.