NVM Matrix Circuits for Memristive Synaptic Weight Computation
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Solution Overview
Problem
Conventional CMOS circuit technologies face scalability issues in implementing synaptic plasticity for neuromorphic computing due to the need for large integrated structures and high costs, especially when attempting to replicate the non-linear phenomena of real synapses, such as spike timing dependent plasticity (STDP).
Innovation Solution
The use of memristors, which are non-volatile, two-terminal electrical devices that mimic the behavior of nonlinear resistors, allowing for the implementation of STDP with a single memristor per synapse and enabling biologically realistic synaptic weight updates, long-term multi-valued weight storage, and weighted pre-synaptic activity communication, thereby relaxing scalability restrictions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional CMOS circuit technology is used to implement synaptic plasticity with STDP, then biologically realistic synaptic weight updates can be achieved, but device complexity and manufacturing cost increase significantly due to requiring about thirty transistors per plastic synapse
Solution Approach 1:
The patent merges multiple functions (synaptic weight storage, plasticity dynamics, and non-linear activation) into a single memristor device. The memristor's resistance state represents synaptic weight, while its intrinsic non-linear I-V characteristics and history-dependent behavior naturally implement STDP-like plasticity and activation functions, eliminating the need for separate transistor circuits for each synapse.
Solution Approach 2:
The patent utilizes changes in the memristor's resistance parameter to represent synaptic weight updates. By controlling the resistance state through applied voltage pulses that mimic pre- and post-synaptic spikes, the system achieves biologically realistic weight modulation without requiring complex transistor-based control circuits.
2Device complexity
If memristors are used to implement synapses, then scalability is greatly relaxed with one memristor per synapse, but sneak path currents and retention issues arise in RRAM technologies
Solution Approach 1:
The patent introduces access transistors as intermediary control elements between the input vectors and memristor arrays. These transistors act as switches that selectively connect or disconnect specific memristors from the circuit during read and write operations, preventing sneak path currents by ensuring only addressed memristors are active during computation.
Solution Approach 2:
The patent implements dynamic control of memristor connectivity through time-dependent switching of access transistors. During different phases of the computation (write vs. read), the transistor states change to either program the memristors or allow them to participate in matrix multiplication, optimizing both scalability and reliability.
3Productivity
If cross-bar connections are used in memristor networks, then matrix multiplication can be performed efficiently, but sneak path currents interfere with computation accuracy
Solution Approach 1:
The patent segments the monolithic cross-bar array into multiple smaller sub-arrays, each with its own set of access transistors. This segmentation allows independent control of different regions, enabling sneak path cancellation techniques where currents from unintended paths can be compensated or subtracted from the final result.
Solution Approach 2:
The patent implements feedback mechanisms where the output currents from the memristor array are read and used to adjust subsequent operations. By measuring and compensating for sneak path contributions through feedback loops, the system maintains computation accuracy while preserving the parallel processing advantages of cross-bar architectures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Memristor-based neuromorphic networks can perform matrix computations efficiently, including weighted matrix multiplication and weight updates, while avoiding sneak path currents and retention issues common in RRAM technologies, thus enhancing the computational capabilities of neural networks.
Implementation Method 1
Each NVM bit cell circuit is configured to couple its resistance to the source line in response to an input voltage applied to its gate node
Implementation Method 2
When the electric power supply is turned off to the memristor, the memristor remembers its most recent resistance until it is turned on again
Implementation Method 3
A memristor's electrical resistance is not constant, but depends on the history of current that had previously flowed through the device
Data Source
AI summary
Non-volatile (NV) memory (NVM) matrix circuits employing NVM circuits for performing matrix computations are disclosed. In exemplary aspects disclosed herein, an NVM matrix circuit is provided that has a plurality of NVM storage string circuits each comprising a plurality of NVM bit cell circuits each configured to store a memory state. Each NVM bit cell circuit has a stored memory state represented by a resistance, and includes a transistor whose gate node is coupled to a word line among a plurality of word lines configured to receive an input vector of 1×m size for example. Activation of the gate of a given NVM bit cell circuit controls whether its resistance is contributed to a respective source line. This causes a summation current to be generated on each source line based on the weighted summed contribution of each NVM bit cell circuit's resistance to its respective source line.