Non-Volatile Memory Power Reset Timing During Active Operations
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Solution Overview
Problem
Non-volatile memory circuits, such as NOR flash memory, are vulnerable to catastrophic data corruption during power cycling due to interruptions during programming or erase operations.
Innovation Solution
Implementing an activity output signal to indicate the activity level of the non-volatile memory circuit, which is used by a power management integrated circuit (PMIC) to determine whether to initiate a power reset, thereby preventing data corruption by ensuring the memory is inactive before powering down.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If power reset is implemented to manage power consumption, then power efficiency is improved, but data corruption risk increases during memory operations
Solution Approach 1:
The patent applies preliminary action by checking the activity status of non-volatile memory before initiating a power reset. The power management integrated circuit (PMIC) determines whether the memory is currently active or inactive, and only proceeds with power reset when the memory is confirmed to be inactive. This prevents power cycle interruptions during programming or erase operations, thereby avoiding data corruption while still enabling power management when safe.
2Reliability
If power reset is delayed to ensure memory is inactive, then data integrity is improved, but power consumption increases due to extended operation time
Solution Approach 1:
The patent implements feedback by continuously monitoring the activity status of the non-volatile memory and using this information to control power reset timing. The PMIC receives feedback about whether the memory is active or inactive, and adjusts the power reset initiation accordingly. This feedback mechanism ensures that power reset only occurs when the memory is inactive, preventing data corruption while minimizing unnecessary delays that would waste power.
Data Source
AI summary
Techniques for protecting non-volatile memory (NVM) from power cycle interruptions during memory operations are disclosed. A power management integrated circuit (PMIC) coupled to a memory circuit with NVM implements the various techniques disclosed. When a power reset signal is asserted to a PMIC, the PMIC may delay initiation of the power reset cycle when it detects that the NVM coupled to the PMIC is active to prevent corruption of the NVM by the power reset cycle. The PMIC may detect the activity level of the NVM based on an activity output signal that indicates whether the NVM is active (e.g., programming or erasing) or inactive.