Non-Volatile Memory Device Segmented Source Leakage Reduction
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Solution Overview
Problem
Conventional non-volatile memory devices, such as EEPROM cells, face challenges with increased resistance and leakage current due to differences in configuration between the common source and drain regions, which affect integration density and signal transmission speed.
Innovation Solution
A non-volatile memory device design featuring serially coupled transistors with a memory cell transistor and a selection transistor, where the transistors are connected between bitlines and have a zigzag bitline configuration, eliminating the common source line and using charge trapping or floating gate structures to reduce resistance and leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a common source region configuration is used in conventional EEPROM cells, then the device structure is simplified, but leakage current increases and resistance increases
Solution Approach 1:
The patent divides the common source region into separate source regions for the memory cell transistor and selection transistor. This segmentation eliminates the leakage current path that existed in the common source configuration, as each transistor now has its own dedicated source region, thereby reducing leakage current while maintaining structural organization.
Solution Approach 2:
The patent extracts the source region from the shared common source configuration and assigns separate source regions to each transistor. This extraction removes the harmful interaction between the memory cell transistor and selection transistor source regions, eliminating the leakage current issue while preserving the simplified structure benefit.
2Quantity of substance
If minimum-sized channel length is used to enhance integration density, then integration density improves, but leakage current and resistance increase due to common source region configuration
Solution Approach 1:
By segmenting the common source region into separate source regions, the patent enables minimum-sized channel length implementation without the leakage penalty. The segmentation isolates the transistors electrically, allowing aggressive scaling for high integration density while maintaining low leakage current through the separate source configurations.
3Adaptability or versatility
If conventional EEPROM cell structure with different source and drain configurations is used, then byte data write/erase capability is achieved, but resistance increases and signal transmission speed decreases
Solution Approach 1:
The segmentation of source regions reduces resistance by eliminating the high-resistance common source configuration. This enables faster signal transmission while preserving the byte data write/erase capability through the maintained transistor configuration and control mechanisms.
Solution Approach 2:
The patent changes the electrical parameters of the transistor configuration by separating the source regions, which reduces resistance and improves signal transmission speed. The data write/erase capability is preserved through appropriate voltage application to the gate and control terminals, demonstrating parameter optimization without functional compromise.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances integration density and reduces leakage current, improving signal transmission speed and storage capacity by allowing for a 2-transistor 2-bit unit cell configuration, doubling storage capacity compared to conventional devices.
Implementation Method 1
The memory cell transistor can include a data storage element having a charge trapping structure
Implementation Method 2
The memory cell transistor can include a data storage element having a floating gate structure
Data Source
AI summary
The present invention is directed to a non-volatile memory device and a method of operating the same. The non-volatile memory device includes a first transistor connected to an nth bitline and a second transistor connected to an (n+1)th bitline. The first transistor and the second transistor are serially coupled between the nth bitline and the (n+1)th bitline. The non-volatile memory device may include a 2-transistor 1-bit unit cell where a drain region and a source region of a memory cell have the same or similar structure. Since a cell array of a non-volatile memory device according to the invention may include a 2-transistor 2-bit unit cell, storage capacity of the non-volatile memory device may be doubled.