Non-volatile Memory Read Speed via Source Line Decoder
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Solution Overview
Problem
Conventional non-volatile memory systems experience increased access time due to prolonged discharging times of the data line during read cycles, which hampers the overall read speed of memory cells.
Innovation Solution
The integration of a source line decoder and a column decoder in the non-volatile memory system, which allows for the selective connection of source lines to a source line voltage and bit lines to a data line, reducing the discharging time of the data line by using a reference voltage, thereby enhancing read speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the data line is discharged during the read cycle, then the memory cell can be read, but the discharging time is prolonged which increases access time
Solution Approach 1:
The patent segments the bit line into two separate lines: a first bit line for reading memory cells in a first column and a second bit line for reading memory cells in a second column. This segmentation allows simultaneous discharge of both bit lines through respective sense amplifiers, effectively halving the access time for multi-column reads while maintaining reliable read capability for each column
Solution Approach 2:
The patent introduces a column selection dimension by adding a second bit line and column decoder, transforming the single-column read operation into a multi-column parallel operation. This dimensional expansion enables simultaneous access to multiple memory columns, reducing overall access time while preserving individual column read reliability
2Productivity
If a source line decoder and column decoder are integrated, then read speed is enhanced by reducing discharging time, but device complexity increases
Solution Approach 1:
The source line decoder is designed to universally control multiple source lines (first source line and second source line) using the same decoding logic and control signals. This multi-functional design enables the decoder to serve multiple columns simultaneously, enhancing read speed across the memory array while avoiding the need for separate decoders for each column, thus limiting the increase in device complexity
3Productivity
If the data line discharging time is reduced, then read speed improves, but the sensing circuit may have insufficient time to accurately detect the memory cell state
Solution Approach 1:
The patent applies preliminary action by pre-charging both the first bit line and second bit line to a known voltage state before the read operation begins. This pre-charging ensures that when the bit lines are discharged during the read cycle, they start from a consistent initial state, allowing the sense amplifiers to quickly and accurately detect the memory cell states without requiring excessive discharge time, thus maintaining sensing accuracy while enabling faster reads
Data Source
AI summary
A non-volatile memory includes a memory array, a row decoder, a source line decoder, a column decoder, and a sensing circuit. The memory array is connected with m word lines, n source lines and n bit lines. The row decoder determines a selected row of n memory cells. The n memory cells in the selected row are connected with the n source lines and the n bit lines. By the source line decoder, an x-th source line is connected with a source line voltage but the other source lines of the n source lines are in a floating state. By the column decoder, an x-th bit line of the n bit lines is connected with a data line but the other bit lines are connected with a reference voltage. The sensing circuit determines a storing state of a selected memory cell.