Non-Volatile Memory Circuit Sub-Array Segmentation

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Solution Overview

Problem

Existing non-volatile memory (NVM) technologies face challenges in data retention, programming endurance, and write disturb, especially in space and power-constrained applications like RFID tags, where a single array is used for diverse memory needs without adequate differentiation.

Innovation Solution

A novel memory circuit architecture that partitions the memory array into sub-arrays with distinct characteristics, each tailored for specific use models, such as data retention, programming endurance, and write disturb immunity, while sharing support circuits to conserve silicon real estate and power.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a single NVM array is used for diverse memory needs, then silicon real estate and power are conserved, but reliability is compromised due to inability to optimize for different use models

Engineering Contradiction:

Improvedata retention and programming enduranceVSAvoidmemory array architecture

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The memory array is divided into multiple sub-arrays, where each sub-array is optimized for specific use models (e.g., data retention, programming endurance, write disturb immunity). This segmentation allows each sub-array to be tailored for its intended purpose while sharing common support circuits, thus improving overall reliability without excessive complexity increase.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Different sub-arrays are constructed with different memory cell characteristics to match specific use models. For example, one sub-array may use cells optimized for data retention while another uses cells optimized for programming endurance. This local quality differentiation enables each portion of the memory to have the optimal properties for its intended function.

Inventive Principle:

Principle #3Local quality

2Reliability

If separate NVM arrays are used for different memory portions, then reliability for specific use models is improved, but silicon real estate and power consumption increase

Engineering Contradiction:

Improveuse model-specific performanceVSAvoidsilicon real estate

Core Design Contradiction:

ReliabilityVSArea of stationary object

Solution Approach 1:

Multiple sub-arrays share common support circuits including sense amplifiers, decoders, and control logic. This merging of support infrastructure reduces the overall silicon real estate required compared to having completely separate arrays, while still maintaining the benefits of differentiated memory cell characteristics for different use models.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The shared support circuits are designed to serve multiple sub-arrays with different characteristics, making the support infrastructure universal and multi-functional. This allows the same support circuitry to work with different memory cell types and configurations, reducing redundancy and saving silicon area.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS8259500B2Non volatile memory circuit with tailored reliability

Publication Date: 2012.09.04 SYNOPSYS INC

AI summary

A non-volatile memory (NVM) circuit is provided, that includes at least a first and second NVM sub-array. The first sub-array is built from first memory cells. The second NVM sub-array is built from second memory cells that are constructed differently from the first memory cells. The NVM sub-arrays share a support circuit. In some embodiments the sub-arrays can be constructed, so that they exhibit different characteristics tailored to their intended use. For example one sub-array might be tailored for data retention, while the next sub-array for programming endurance, still another for write disturb immunity.