Non-Volatile Memory Program Voltage Adjustment for Cell Disturbance
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Solution Overview
Problem
Non-volatile memory devices face reliability issues due to disturbances between neighboring memory cells during program operations using the incremental step pulse program (ISPP) method, which existing technologies have not adequately addressed.
Innovation Solution
A method and device that execute multiple program loops on memory cells, generate a fail bit trend based on the results of these loops, predict the number of program loops including the last loop, and adjust the program voltage level for the last loop based on the prediction to minimize disturbances.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the incremental step pulse program (ISPP) method is used to perform program operations on memory cells, then the program operation can be completed, but disturbance between neighboring memory cells is caused
Solution Approach 1:
The patent applies preliminary action by predicting the number of program loops needed before executing the full program operation. The control logic generates a fail bit trend based on initial program loop results, predicts the total loops required, and then adjusts subsequent program voltages accordingly. This preliminary prediction allows the system to prepare appropriate voltage levels in advance, preventing disturbance to neighboring cells before it occurs.
Solution Approach 2:
The patent implements dynamics by making the program voltage level adjustable based on real-time feedback. The control logic dynamically changes the program voltage level for subsequent loops based on the predicted number of program loops and fail bit trends. This dynamic adjustment allows the system to optimize each program loop's voltage level, reducing unnecessary high-voltage applications that cause disturbance while ensuring complete programming.
2Reliability
If multiple program loops are executed on memory cells, then programming reliability can be improved, but program time increases
Solution Approach 1:
The patent applies feedback by using the results of executed program loops to generate a fail bit trend, which then informs the prediction of total loops needed. The control logic continuously monitors program operation results and adjusts the predicted loop count accordingly. This feedback mechanism allows the system to determine the minimum necessary number of loops for reliable programming, avoiding unnecessary additional loops that would increase program time without improving reliability.
Solution Approach 2:
The patent implements parameter changes by adjusting the program voltage level based on the predicted number of program loops. When fewer loops are predicted, higher voltage levels can be used to accelerate programming. When more loops are needed, lower voltage levels prevent disturbance. This parameter adjustment optimizes the balance between programming speed and reliability, ensuring adequate programming in fewer loops when possible while maintaining reliability when more loops are required.
Data Source
AI summary
A method of programming a non-volatile memory includes executing at least two program loops on memory cells in a selected word line, generating a fail bit trend based on a result of executing each of the at least two program loops, predicting a plurality of program loops comprising an N program loop to be executed last on the memory cells, based on the generated fail bit trend, and changing, based on a result of predicting the plurality of program loops, a level of an N program voltage provided to the memory cells when the N program loop is executed.